Samsung Electronics Co., Ltd.

International Business Machines Corporation

Infineon Technologies Ag

Freescale Semiconductor,inc.

Globalfoundries Singapore Pte. Ltd.

Infineon Technologies North America Corp.

Yong-Kuk Jeong

Seok-Jun Won

Weon-hong Kim

Dae-Jin Kwon

Min-Woo Song

Dong-Suk Shin

Dae-jin Kwon

Cha-young Yoo

Myong-geun Yoon

Jae-Hyun Joo

Jung-Hyoung Lee

Jung-min Park

Andrew-tae Kim

Ki-chul Kim

Sang-Wook Park

Oh-Jung Kwon

Ha-Jin Lim

Wan-don Kim

Min-Hee Choi

Hong-Ki Kim

Se-hoon Oh

Dong-Hyun Roh

Eun-ae Chung

Laegu Kang

Jung-hee Chung

Pan-Kwi Park

O Sung Kwon

Wan-Don Kim

Seong-Dong Kim

Moon-Han Park

Doo-sup Hwang

Bong-Seok Suh

Ho-Kyu Kang

Weon-Hong Kim

Jung-Shik Heo

Andrew Tae Kim

Dae-won Yang

Dong-Hee Yu

Il-young Yoon

Kyung-Hun Kim

Kim Nam Sung

A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si&#x2014;H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.

Method of forming semiconductor device using Si-H rich silicon nitride layer

Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.

Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment

A semiconductor device includes a substrate, a gate structure disposed on the substrate and which includes a gate insulating layer and a gate electrode layer, a first nitride layer disposed on the substrate and the gate structure and which includes silicon, and a second nitride layer that is disposed on the first nitride layer and has an atomic percentage of silicon less than that of the first nitride layer.

Semiconductor device

A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si&#x2014;H bond and/or a Ge&#x2014;H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.

Methods of manufacturing CMOS transistors

Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Semiconductor devices including dehydrogenated interlayer dielectric layers

A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.

Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same

Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.

Analog capacitor

Methods of manufacturing semiconductor devices

Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance

A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

Method of forming a carbon nano-material layer using a cyclic deposition technique

A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

Semiconductor device and methods of fabricating the same including forming spacers and etch stop layers with stress properties

In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method

A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.

Shallow trench isolation structures for semiconductor devices including wet etch barriers

An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.

Analog capacitor and method of manufacturing the same

In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.

Method of fabricating trench isolation of semiconductor device

Growing community of inventors

Seoul, South Korea

Yong-Kuk Jeong