Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Yong Koon Lee

Myung Sam Kang

Young Gwan Ko

Young Chan Ko

Yong Jin Seol

Jin Su Kim

Chang Bae Lee

Sang Kyu Lee

Jin Gu Kim

Moon Il Kim

A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.

Semiconductor package and antenna module comprising the same

A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer.

Semiconductor package

A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Semiconductor package and antenna module including the same

An antenna module includes an antenna substrate having a first surface and a second surface disposed to oppose each other, and including a substrate wiring layer having a first antenna pattern positioned in a first region, a second antenna pattern disposed in a second region adjacent to one side, and first and second feed patterns connected to the first and second antenna patterns, respectively; and a semiconductor package including a connection structure disposed on the second surface except for an area overlapping with the second region of the antenna substrate and redistribution layers electrically connected to the substrate wiring layer, and at least one semiconductor chip having connection pads connected to the redistribution layers. A region overlapping with the second feed pattern in each of the plurality of redistribution layers is provided as an opened region.

Antenna module

A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.

A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.

A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

Fan-out semiconductor package module

A fan-out semiconductor package includes a redistribution layer, the redistribution layer including a first insulating layer, a first wiring disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first wiring, a line via passing through the second insulating layer continuously and connected to the first wiring, and a second wiring disposed on the second insulating layer and connected to the line via; a semiconductor chip disposed on one side of the redistribution layer, and having an electrode pad electrically connected to the first wiring, the second wiring, and the line via; and an encapsulant disposed on the one side of the redistribution layer, and encapsulating the semiconductor chip.

Growing community of inventors

Suwon-si, South Korea

Yong Koon Lee