Samsung Electronics Co., Ltd.

Other

Yong Ki Lee

Sun-Soo Shin

Jonghoon Shin

Kyoungmoon Ahn

Bohdan Karpinskyy

Yunhyeok Choi

Ji-su Kang

Yongsoo Kim

Mijung Noh

Jaehyeok Kim

Taewook Park

Gapkyoung Kim

Dong Jin Park

Yong Woo Lee

Sang Hyun Park

Ji Yeun Kim

Sang Kyun Kim

Sang-wook Park

Yong Ju Jung

Jin Guk Jeong

Yun-Ho Youm

Eunhye Oh

KeeMoon Chun

Hyungdong Roh

Kee Moon Chun

Hyochul Shin

Heon Soo Lee

Eui Hyeon Hwang

Jinsu Hyun

Heui Sam Lee

Kyoung Moon Ahn

Mi Jung Noh

Hyun Bok Kim

Sun Yeou Kim

San Ko

Sung-No Lee

Hong-Mook Choi

Woo Hyung Chun

Hong Mook Choi

Soo-Ho Lim

Woon-Young Choung

Kang-Sun Ryu

Cheol Kon Jung

Doo Sun Hwang

Ji-Su Kang

KyoungMoon Ahn

A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.

Built-in-self-test logic, memory device with same, and memory module testing method

Disclosed is an electronic device which includes an audio processing block for voice recognition in a low-power mode. The electronic device includes a digital microphone that receives a voice signal from a user and converts the received voice signal into a PDM signal, and a DMIC interface circuit. The DMIC interface circuit includes a PDM-PCM converting block that converts the PDM signal into a PCM signal, a maxscale gain tuning block that tunes a maxscale gain of the PCM signal received from the PDM-PCM converting block based on a distance information indicating a physical distance between the user and the electronic device acquired in advance of the converting of the PDM signal, and an anti-aliasing block that performs filtering for acquiring voice data of a target frequency band associated with a PCM signal output from the maxscale gain tuning block.

Digital microphone interface circuit for voice recognition and including the same

A key enrollment method of a physically unclonable function (PUF) circuit including a plurality of PUF cells includes receiving a first level key from PUF cells, performing bit encoding on the first level key using a bit coding table based on Hamming weights of a plurality of bits in the first level key to generate a second level key, storing first helper data associated with the second level key in a non-volatile memory, performing block encoding on the second level key using an error correction code to generate a third level key, and storing second helper data associated with the third level key in the non-volatile memory.

Physically unclonable function circuits and methods of performing key enrollment in physically unclonable function circuits

A semiconductor device includes a physical unclonable function (PUF) cell array that includes PUF cells outputting first bits; a non-volatile memory that stores marking bits indicating whether the first bits are valid, first mask bits generated by masking second bits depending on parity of the second bits, and second mask bits generated by masking helper bits of the second bits, the second bits are valid bits from the first bits; an extracting unit that extracts the second bits from the first bits using the marking bits; an unmasking unit that unmasks the second bits using the first mask bits while receiving the second bits to provide the third bits; a bit decoding unit that compresses the third bits to fourth bits while receiving the third bits; and a block decoding unit that generates a security key by decoding the fourth bits and the second mask bits.

Semiconductor device generating security key, method of generating security key, and method of enrolling security key

A semiconductor device may include: a bus; first and second function modules configured to communicate via the bus; a first encryption module configured to encrypt first data output from the first function module using a first encryption key to generate first encrypted data; and/or a second encryption module configured to decrypt the first encrypted data using the first encryption key, to output the decrypted first data to the second function module, and to encrypt second data output from the second function module using a second encryption key to generate second encrypted data. A semiconductor device may include: a bus; first and second modules configured to communicate via the bus; and/or an encryption module configured to use different encryption policies for first data, which is output from the first module and stored in a memory, and second data, which is output from the second module and stored in the memory.

Semiconductor devices and methods of protecting data of channels in the same

A random number generator may include a first meta-stable inverter having an input terminal and an output terminal connected to each other and configured to generate a meta-stable voltage, an amplifier configured to amplify the meta-stable voltage, control circuitry configured to adjust a threshold voltage of the meta-stable voltage, and a sampler configured to generate a random number based on sampling the meta-stable voltage. The random number generator may be configured to be operated according to different modes of operation of a plurality of modes of operation. The amplifier may be a second meta-stable inverter configured to amplify the meta-stable voltage or include an input terminal and an output terminal that are connected to each other based on the random number generator being operated according to a first mode of operation or a second mode of operation, respectively, of the plurality of modes of operation.

Random number generators and methods of generating random numbers using adjustable meta-stable voltage

A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.

Modular multiplier and modular multiplication method thereof

A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.

Montgomery multiplication method for performing final modular reduction without comparison operation and montgomery multiplier

A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Encoder and method for encoding thereof

A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.

Device having secure JTAG and debugging method for the same

A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.

Multiplication method and modular multiplier using redundant form recoding

A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.

Modular arithmatic unit and secure system including the same

Growing community of inventors

Yongin-si, South Korea

Yong Ki Lee