Skhynix Inc.

Korea Advanced Institute of Science and Technology

Yong-Kee Kwon

Hong-Sik Kim

Young-Suk Moon

Hyung-Dong Lee

Hyung-Gyun Yang

Dong-Gun Kim

Yong-Ju Kim

Won-Gyu Shin

Lee-Sup Kim

Jung-Whan Choi

Do-Sun Hong

John Dongjun Kim

Sang-Gu Jo

Joon-Woo Kim

Young-Ook Song

Gwangsun Kim

A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Memory system including memories having different characteristics and operation method thereof

A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Memory network and system including the same

A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

Semiconductor device with temporary memory chip and method for driving the same

A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

System and method for operating the same

A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Memory controller

A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Cache device and control method threreof

A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

Memory controller scheduling requests according to scores

A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Semiconductor device for performing test and repair operations

A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.

Data storage device and operating method thereof

A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.

Semiconductor device

A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.

Semiconductor device and operating method thereof

A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue.

A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to one or more second signal lines adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and restore data in one or more cells of the cells connected to the second signal line when determining that there is the data damage risk.

A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.

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Seoul, South Korea

Yong-Kee Kwon