Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Spansion Llc.

Yong K Kim

Lee Edward Cleveland

Kendra Nguyen

Takao Akaogi

Ali K Al-Shamma

Boon Tang Teh

Jin-Lien Lin

Yasushi Kasa

Mark Alan McClain

Keith H Wong

A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.

Data refresh in non-volatile memory

The physical layout of a semiconductor memory device having memory sectors of varying sizes can be arranged such that the larger and smaller memory sectors are addressed by x-decoders and y-decoders via word lines and bit lines, respectively. The smaller memory sectors are laid out such that some of the small memory sectors are connected with a y-decoder or multiple y-decoders via different bit-lines. The smaller memory sectors are interspersed with the large memory sectors and an area near a corner of the memory device that can be used for other components such as peripheral devices. Optional physical to logical mapping of address allow the smaller memory sectors to be addressed in the first or the last memory addresses.

Physical memory layout with various sized memory sectors

A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Memory line discharge before sensing

An integrated circuit ( ) has an input ( ) for receiving an externally applied power supply voltage. Internal to the integrated circuit, a pass transistor ( ) conveys the supply voltage to an internal supply node ( ) which supplies the operating circuitry ( ) of the integrated circuit. The pass transistor has a relatively low threshold voltage for operation at reduced supply voltage, such as 1.0 volt. The pass transistor is controlled by an enable signal received at an input ( ) and by a charge pump ( ). In a standby mode, the charge pump raises the voltage on the gate of the pass transistor to fully turn off the pass transistor and minimize standby current.

Low threshold voltage device with charge pump for reducing standby current in an integrated circuit having reduced supply voltage

A non-volatile semiconductor memory device comprising a memory array, the memory array divided into a plurality of sectors, each sector comprising a plurality of memory cells, which can be electrically erased, and an erase-verify circuit, capable of simultaneously erasing multiple memory sectors. The erase-verify circuit simultaneously erases a plurality memory sectors, and verifies that the memory cells in a selected memory sector of the plurality of memory sectors is erased. When it determines that the selected memory sector is not erased, it again erases the plurality of memory sectors and again verifies whether the selected memory sector is erased. The erasing of the plurality of memory sectors is repeated until it is verified that the memory cells in the selected memory sector is erased.

Fast-erase memory devices and method for reducing erasing time in a memory device

A voltage boost circuit ( ) for a flash memory ( ) includes a boosting circuit ( ), which is capable of boosting a portion of a power supply voltage (V ) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array ( ) of the memory. The voltage boost circuit further includes a balancing or clamping circuit ( ) for providing a nonzero adjustment voltage (V ) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Voltage boost level clamping circuit for a flash memory

A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.

Word line decoding architecture in a flash memory

An improved level shifter circuit is provided which is designed for use with an extremely low power supply voltage. The level shifter circuit includes a fourth NMOS transistor, a third PMOS transistor, and a fifth NMOS transistor connected in series and interconnected between the high voltage and the output terminal. As a result, the high voltage will still be passed to the output terminal when the high voltage is lowered to be equal to the low power supply voltage.

Level-shifter for extremely low power supply

A reference voltage generator circuit is provided for use with an extremely low power supply voltage. The reference voltage generator circuit produces a lower reference output voltage which is compensated for temperature variations and is independent of changes in the supply voltage. The reference output voltage relies upon the threshold voltage V.sub.T of a MOSFET transistor as a reference source.

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Santa Clara, CA, United States of America

Yong K Kim