Samsung Electronics Co., Ltd.

Electronics and Telecommunications Research Institute

Yong-June Kim

Jae-Hong Kim

Jun-Jin Kong

Jaehong Kim

Young-Hwan Lee

Jong-Seon No

Sunghwan Kim

Junjin Kong

Jae-Young Ahn

Seung-Hwan Song

Sang-Hyun Lee

Kyoung-Lae Cho

Yun-Hee Kim

Hee-seok Eun

Kijun Lee

Dong-Hyuk Chae

Hong-Rak Son

Eun-chu Oh

Ki-Jun Lee

Jong-han Kim

Han Woong Yoo

Sejin Lim

Han-woong Yoo

Beom-kyu Shin

Ho-sung Park

A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

Data processing systems and methods providing error correction

An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Interleaving apparatuses and memory controllers having the same

A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.

Method of operating memory controller, and memory system, memory card and portable electronic device including the memory controller

An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

Semiconductor device and decoding method thereof

Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes the following steps: (a) the nodes are divided according to a parity-check matrix into check nodes for a parity-check message and variable nodes for a bit message; (b) the check nodes are divided into a predetermined number of subsets; (c) the LDPC codeword of each subset for all the check nodes is sequentially decoded; (d) an output message is generated for verifying validity of the decoding result; and (e) the steps (b), (c), and (d) are iteratively performed by a predetermined number of iterations.

Decoding apparatus for low-density parity-check codes using sequential decoding, and method thereof

Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

Memory systems and defective block management methods related thereto

A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

Decoding method and memory system device using the same

The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nbits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nbits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nbits of the data are completely programmed or read, programs or reads an (N+1)bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nbits of the data, to program or read for 2cell distributions of 2cell distributions corresponding to the (N+1)bit of the data and then programs or reads for other 2cell distributions.

Flash memory device, programming and reading methods performed in the same

Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same

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Seoul, South Korea

Yong-June Kim