Samsung Electronics Co., Ltd.

Other

Yong-jun Lee

Hoi-ju Chung

Hyo-Jin Kwon

Yong-Jin Kwon

Eun-Hye Park

Chea-Ouk Lim

Moo-sung Kim

Eun-chu Oh

Jeong-ho Lee

Tae-Hui Na

Young-Sik Kim

Hye-Young Ryu

Makoto Hirano

Kyung-Tae Lee

Yoon-Hae Kim

Kyung-Chang Ryoo

Kwang Jin Lee

Bilal Ahmad Janjua

Joon Min Park

Joon-Yong Choi

Young-sik Kim

Chae-Hoon Kim

Jun-Gyu Lee

Jin-gee Kim

Yu Hwan Ro

Byunggil Choi

Huik Won Seo

Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Method of equalizing bit error rates of memory device

A refill container removably stored in a cosmetic compact includes: a main body being open at an upper part thereof and having a housing space inside thereof, an upper end sealing protrusion part, a lateral sealing protrusion part provided at an outer surface of the inner wall, and an outer wall being provided outside the inner wall with a predetermined gap therebetween; and a mesh fabric cover having a cylindrical first vertical extension part combined with the inner wall and the outer wall by being inserted into a gap provided therebetween such that an inner surface of the first vertical extension part is in close contact with the lateral sealing protrusion part, and a first rim part provided at an upper end of first vertical extension part.

Refill container for cosmetic compact

A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Memory devices, memory systems and methods of operating memory devices

An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Resistive memory devices having address-dependent parasitic resistance compensation during programming

Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Method of operating resistive memory device capable of reducing write latency

A nonvolatile memory device includes a buffer memory, a read circuit configured to read first data stored in the buffer memory in a first read operation, and a write circuit configured to write second data in the buffer memory in a first write operation, wherein the first write operation is performed when a first internal write command is generated during the first read operation.

Nonvolatile memory device using a resistance material and a driving method thereof

A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation

A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.

Nonvolatile memory device and related method for reducing access latency

The present invention relates to a dispenser for supplying a disposable paper product of a roll type such as a toilet paper, a hand towel and etc. The dispenser has a main body casing which accommodates the paper product and has a rotating shaft supporting the paper product to be rotatable and a discharging part for discharging the paper product, and a wet type cutting unit which is located at the discharging part to provide liquid to a part of the paper product that is to be cut. Liquid is provided to an area of the paper product to be cut, so that the paper product can be easily cut with a relatively small force.

Dispenser

A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Nonvolatile memory device comprising one-time-programmable lock bit register

A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Nonvolatile memory device and method for controlling word line or bit line thereof

In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.

Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same

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Hwaseong-si, South Korea

Yong-jun Lee