Samsung Electronics Co., Ltd.

Snur & Db Foundation

Lg Chemical Ltd.

Lg Chem-investment Ltd.

Newfrontech Co., Ltd.

Yong-Jun Lee

Woo-Yeong Cho

Kwang-Jin Lee

Jeong-Hoon Ahn

Taek-Sung Kim

Du-Eung Kim

Hye-Jin Kim

Kyoung-woo Lee

Kwang-Ho Kim

Kyung-Tae Lee

Hyun-Ho Choi

Il-Goo Kim

Qi Wang

Soo-Geun Lee

Hong-Kyun Lee

Wan-Jae Park

Mu-Kyeng Jung

Byung-Gil Choi

Jaejin Lee

Kwangho Kim

Moo-sung Kim

Hye Jin Kim

Kwangjin Lee

Joon-Yong Choi

Seung-Mo Cho

Kyuboem Han

Young-sik Kim

Yong-Ho Park

Wooyeong Cho

Kyungtae Lee

Hyunho Choi

Gangwon Jo

Jin-gee Kim

Hongjune Kim

Jeongho Nah

Honggyu Kim

Kyu-Boem Han

Byoung-Sun Chang

Mu-Kyung Jung

Joo-Hwan Lee

Lee Jeong-Ho

Eun-Chu Oh

Jin-Gee Kim

A web browsing method and apparatus for enhancing a user's convenience in web browsing is provided in a system that uses a multi-core processor. The web browsing method and apparatus is applicable in a system, such as a smart phone that has a low computing power or that has a storage device like a flash memory operating in a rapid manner. Optimized machine codes are stored in files and incremental optimization is achieved, so the JAVASCRIPT&#xae; program of the web application has a small compilation overhead and achieves fast execution.

Web browsing apparatus and method through storing and optimizing JAVASCRIPT&#xae; code

In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.

Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation

In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Semiconductor device having resistance based memory array and method of operation associated therewith

Semiconductor device having resistance based memory array, method of operation, and systems associated therewith

Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Variable resistance memory device and system

Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Method of preventing coupling noises for a non-volatile semiconductor memory device

Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Integrated circuit capacitor structure

Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

The present invention relates to a method of producing recombinant modified Staphylococcal toxin having improved stability, comprising the steps of preparing a modified toxin in which a specific amino acid sequence is substituted and a vector for expressing the modified toxin, and culturingtransformed with the vector, and a use thereof for the vaccine.

Staphylococcal enterotoxin SEC-SER, expression vector and host cell, production method thereof, and manufacturing method of vaccine

A process for the preparation of biologically active somatotropin from inclusion bodies of a recombinant host cell containing an inactive form of said somatotropin protein comprises the steps of:

Process for the preparation of active somatotropin from inclusion bodies

Growing community of inventors

Anyang-si, South Korea

Yong-Jun Lee