Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Mvrix Co., Ltd.

Yong-Jun Kim

Tae-Kyoung Kang

Dae-Won Kim

Ho Tae Jin

Min-Sun Yoo

Cha-Keun Yoon

Chi-Sung Oh

Kyung-Woo Nam

Jeong-Hyun Seo

Eun-Jung Kim

Soo-Young Kim

Seung-Pil Ko

Jin-Kuk Kim

Ki-Jung Kim

Dong-Hyuk Lee

Dong-sik Shim

Kyu-Chan Lee

Jong-wook Park

Ki-Joon Kim

Sung-hee Kim

Mi-Hyun Son

Jae-Kyu Lee

Jung-Keun Ahn

Jong-Wook Park

Woo-Seop Jeong

Sung-Hune Yoo

Kil-Ho Lee

Jae-Kwon Kim

Jae-Rok Kahng

Sang-goog Lee

Myoung-Su Son

Dae-Hyuk Kweon

Sung-In Kim

Jung-Yon Cho

Goo Jun

Tae-Ho Lee

Eun-Jung Kang

Eu-gene Choi

Jung-Woo Song

Myung-Bo Kwak

Young-Mi Kang

Min-Ju Kim

Won-beom Park

Joon-Bum Park

Bong-Yen Kim

Dong-Wook Kang

Hyo-Dae Kim

Yu-Seong Jeon

The present invention relates to a method for producing botulinum toxin in various fragments to then be reassembled, for safely producing same. In the present invention, devised is a method in which: botulinum toxin is produced in fragments by cleaving light and heavy chains thereof into two or three pieces, respectively, and then combined as a full-length toxin, thereby allowing high complexity in production, due to toxicity, as well as low safety and economic feasibility, to be overcome; production of water-soluble botulinum toxin is enabled by using bacteria, thereby markedly shortening the production time as compared to existing production methods; and conjugation of the produced fragments with other proteins and nanoparticles is also enabled, thereby increasing the pharmaceutical extensibility of the toxin.

Method for safely producing botulinum neurotoxin

Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

Semiconductor devices having buried contact structures

Disclosed is an apparatus for controlling an AV device, comprising a web browser receiving a structured document to contain a script from the AV device, and providing the same to a user, and a first program module including a function called by the script and transmitting information on a device control command to the AV device through a protocol previously defined by use of the function, wherein the AV device comprises a web server module transmitting the structured document and a second program module receiving the device control command information from the first program module through the protocol and controlling the AV device in response to the command information.

Audio/video device, apparatus and method for controlling audio/video device

A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.

Semiconductor device including a diode and method of manufacturing the same

A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.

Method of manufacturing a semiconductor device

Provided are a method of forming a contact and a method of manufacturing a phase change memory device using the same. The method of forming a contact includes forming on a substrate an insulating layer pattern having first sidewalls extending in a first direction and second sidewalls extending in a second direction perpendicular to the first direction and which together delimit contact holes, forming semiconductor patterns in lower parts of the contact holes, forming isolation spacers on the semiconductor pattern and side surfaces of the first sidewalls to expose portions of the semiconductor patterns, and etching the exposed portions of the semiconductor patterns using the isolation spacers as a mask to divide the semiconductor patterns into a plurality of finer semiconductor patterns.

Method of forming a contact and method of manufacturing a phase change memory device using the same

A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Method, device, and system for preventing refresh starvation in shared memory bank

A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof

Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

Semiconductor memory device and test method thereof

A plasma display panel includes a first substrate and a second substrate, the first substrate and the second substrate being provided with a predetermined gap therebetween. Barrier ribs are formed in a non-striped pattern between the first substrate and the second substrate, the barrier ribs defining a plurality of discharge spaces. A plurality of address electrodes are formed on the first substrate along a direction (y), the address electrodes being formed within and outside discharge spaces. A plurality of sustain electrodes are formed on the second substrate along a direction (x), the sustain electrodes being formed within and outside discharge spaces. The address electrodes include large electrode portions provided within discharge spaces and small electrode portions provided outside the discharge spaces. If a width of large electrode portions is AW, a width of small electrode portions is Aw, and a distance between barrier ribs along direction (x) is D, AW is larger than Aw, and AW is 40-75% of D.

Plasma display panel having discharge cells

A plasma display panel design having a display area and a peripheral area surrounding the display area. Within the display area are discharge cells, and within the peripheral area are dummy cells that serve as a location where fluorescent paste is injected onto in an early stage of making the display, enabling the injection amount and injection speed from a nozzle to stabilize before the fluorescent material is deposited into the discharge cells. A surface area that the fluorescent material is deposited on in the peripheral area is increased to provide for a more rapid stabilization of the injection pressure and injection amount of the paste in the making of the display. A sufficient gap is present between a sealant and the dummy structure so that air and foreign matter can be expelled.

Plasma display panel

Temperature detectors include a temperature sensor that is configured to generate temperature tracking signals that indicate that a detected temperature is above, below or in a temperature range that corresponds to a selected one of a series of temperature control signals that indicate a series of temperature ranges. A control circuit is configured to sequentially supply the selected one of the series of control signals to the temperature sensor in response to the temperature tracking signals. The series of temperature control signals may indicate a series of overlapping temperature ranges, such that the temperature detector has a hysteresis characteristic. Analogous methods also may be provided.

Sequential tracking temperature sensors and methods

A plasma display panel includes designed to improve optical efficiently and to reduce misdischarging between discharge cells. The address electrodes have varying widths so that they are narrow in discharge cells and are relatively wide outside of discharge cells. Discharge gas filling the discharge cells have an elevated Xe content, preferably 10 to 30%. Other variations further include having striped and matrix patterned barrier ribs, forming the discharge sustain electrodes in tabs extending in pairs into the middle of the discharge cells, and varying the width of address electrodes at various locations outside of the discharge cells.

A plasma display panel includes a first substrate and a second substrate, the first substrate and the second substrate being provided with a predetermined gap therebetween. Barrier ribs are formed in a non-striped pattern between the first substrate and the second substrate, the barrier ribs defining a plurality of discharge spaces. A plurality of address electrodes are formed on the first substrate along a direction (y), the address electrodes being formed within and outside discharge spaces. A plurality of sustain electrodes are formed on the second substrate along a direction (x), the sustain electrodes being formed within and outside discharge spaces. The address electrodes include large electrode portions provided within discharge spaces and small electrode portions provided outside the discharge spaces. If a width of large electrode portions is AW, a width of small electrode portions is Aw, and a distance between barrier ribs along direction (x) is D, AW is larger than Aw, and AW is 40&#x2013;75% of D.

Plasma display panel having delta discharge cell arrangement

Growing community of inventors

Suwon-si, South Korea

Yong-Jun Kim