Intel Corporation

Yong Ju Lee

Jack T Kavalieros

Gilbert W Dewey

Marko Radosavljevic

Willy Rachmady

Niloy Mukherjee

Prashant Majhi

Wilman Tsai

Niti Goel

Brian S Doyle

Uday Shah

Kaan Oguz

Charles C Kuo

David L Kencke

James Nadir

Nagraj Palasamudram

Roksana Golizadeh Mojard

Niti Goe

Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Conductivity improvements for III-V semiconductor devices

A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening.

Method for reducing size and center positioning of magnetic memory element contacts

A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is extended by a pending tag RAM access. At any time, except when the next cycle has started, but during which the current cycle is in progress, one latch is open to an input buffer such that the input address is latched by that latch. The other latch holds the current cycle address until the cycle ends. The current cycle can be extended with snoops. The current cycle address has to be maintained as long as the cycle is still in progress. In the meantime, the external cycle might have ended and a next cycle started. The second address latch is used to capture the address corresponding to this new cycle. As signal selects which of the two latches will supply the address via a MUX to the tag RAM. Logic switches the two input address latches so that the tag RAM sees a constant address for the duration of a cycle while at the same time a new cycle address can be received.

Cache controller that alternately selects for presentation to a tag RAM

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Sunnyvale, CA, United States of America

Yong Ju Lee