Skhynix Inc.

Hynix Semiconductor Inc.

Postech Academy-industry Foundation

Korea University Research and Business Foundation

University of Seoul Industry Cooperation Foundation

Yong Ju Kim

Hae Rang Choi

Jae Min Jang

Hyung Soo Kim

Tae Jin Hwang

Ic Su Oh

Hee Woong Song

Ji Wang Lee

Donggun Kim

Sung Woo Han

Chang Kun Park

Sang Gu Jo

Dae Han Kwon

Do-Sun Hong

Kun Woo Park

Do Sun Hong

Jong Woon Kim

Jung Hyun Kwon

Seong Hwi Song

Jae Sun Lee

In Hwa Jung

Sungeun Lee

Jingzhe Xu

Chul Woo Kim

Hae Kang Jung

Hong June Park

Dong Yoon Kim

Jong Ho Son

Jae Yoon Sim

Won Joo Yun

Jong Ho Jung

Su Hae Woo

Hyun Seok Kim

Yong S Moon

Soo Min Lee

Min Seob Lee

Soo Mln Lee

Hee Wong Song

Kil Ho Cha

Dan Han Kwon

Jong Gon Jung

A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

System and method for repairing memory

A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Methods, semiconductor devices, and semiconductor systems

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

Test apparatus

A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Resistance variable memory apparatus, and circuit and method for operating therefor

A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

Memory system including a delegate page and method of identifying a status of a memory system

An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

Apparatuses and methods of distributing addresses in memory devices for mitigating write disturbance

A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

Memory apparatus and method of wear-leveling of a memory apparatus

A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

Semiconductor systems

A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Data transmission apparatus, data reception apparatus, data transmission and reception system

A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Memory controllers, memory systems, and methods relating to wear-leveling

Growing community of inventors

Icheon-si, South Korea

Yong Ju Kim