Hynix Semiconductor Inc.

Skhynix Inc.

Industry-university Cooperation Foundation Hanyang University

Samsung Electronics Co., Ltd.

Hynic Semiconductor Inc.

Yong-Ju Kim

Hae-Rang Choi

Ic-Su Oh

Hyung-Soo Kim

Tae-Jin Hwang

Hee-Woong Song

Jae-Min Jang

Ji-Wang Lee

Chang-Kun Park

Sung-Woo Han

Kun-Woo Park

Dae-Han Kwon

Do-Sun Hong

Sang-Gu Jo

Dong-Gun Kim

Jung-Hyun Kwon

Shin-Deok Kang

Jong-Woon Kim

Oh-Kyong Kwon

Sung-Eun Lee

Kang-Sub Kwak

Taek-Sang Song

Hong-Sik Kim

Yong-Kee Kwon

Young-Ook Song

Jun-Yong Song

Hyeon-Cheon Seol

Kyung-min Lee

Hyung-Gyun Yang

Jing-Zhe Xu

Joon-Woon Kim

Ki-Joong Kim

Kyung-Hoon Kim

Jun-Ho Lee

Jun-Woo Lee

Sang-sung Woo

Jae-Il Kim

Seong-Jun Lee

Jong-chan Kwon

Kwan-Weon Kim

Jae-Sun Lee

Chang-Kyu Choi

Myeong-Jae Park

Ji-yeon Shin

Han-Kyu Chi

Youk-Hee Kim

Young-ei Cho

Woo-Yeol Shin

Jong-Hyun Ra

Seong-hun Ahn

Se-o Lee

Soo-yeun Yang

Yang-jic Lee

A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Semiconductor system and method for operating the semiconductor system

A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Memory system and wear-leveling method using the same

A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

Memory system and error correcting method thereof

A management server is provided. The management server includes a communication interface unit configured to receive user environment information from a plurality of wearable apparatuses located in a preset space, an analyzer configured to analyze an environment state of the preset space based on a plurality of pieces of the received user environment information regarding the plurality of wearable apparatuses and determines an operation state of a common device located in the preset space according to the analyzed environment state, and a controller configured to control the communication interface unit so as to operate the common device according to the determined operation state.

Wearable apparatus, management server, management system having the same, and method for controlling thereof

A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Memory system for controlling read voltage using cached data and operation method of the same

A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Memory system including memories having different characteristics and operation method thereof

A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

Memory system and operating method thereof

A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

Semiconductor device with temporary memory chip and method for driving the same

A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

Memory system and method for wear-leveling by swapping memory cell groups

A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

Memory system and method for operating the same

A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

System and method for operating the same

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Clock generation circuit

A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

Memory system including memory controller and operation method thereof

A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

Memory device using extra read and write commands

A robot cleaner is provided that includes a driver configured to move the robot cleaner, and a suction unit configured to suck foreign objects from a surface below the robot cleaner. The robot cleaner also includes a detector configured to capture images of regions disposed in front of the robot cleaner. The robot cleaner further includes a controller configured to control the detector to capture a first image of a region before cleaning, control the detector to capture a second image of the region after cleaning, and generate cleaning result information using the first and second images.

Robot cleaner, terminal apparatus, and method of controlling the same

Growing community of inventors

Gyeonggi-do, South Korea

Yong-Ju Kim