Samsung Electronics Co., Ltd.

Yong-joon Jung

Yong-in Han

Seok-joon Park

Kwang-whui Cho

Gwang-sun Lee

Hwan-sang Roh

In a sync processor for determining safety of signals on the basis of a horizontal/vertical sync signal generated according to a data enable signal, the sync processor includes a digital horizontal/vertical signal generator, a selector, a digital horizontal/vertical signal detector, a horizontal/vertical polarity determination unit, and a horizontal/vertical frequency determination unit. The digital horizontal/vertical signal generator generates a digital horizontal/vertical sync signal from the data enable signal. The digital horizontal/vertical signal detector detects a signal received from the selector and generates a digital horizontal/vertical signal. The horizontal/vertical polarity determination unit counts the number of low and high durations of a horizontal/vertical sync signal and generates a horizontal/vertical polarity signal in response. The horizontal/vertical frequency determination unit counts the number of cycles of the clock signal occurring in low and high durations of a digital horizontal/vertical polarity signal and generates a horizontal/vertical frequency signal in response.

Sync processor of flat panel display for determining signal safety on the basis of HSYNC/VSYNC signal generated according to data enable signal

A response time accelerator and method for driving a liquid crystal display (LCD) are provided. According to the response time accelerator for driving an LCD, an acceleration unit reads previous data Pn&#x2212;1 corresponding to input current data Pn from a frame memory unit that updates and stores one or more frames of previous data Pn&#x2212;1. The acceleration unit then reads predetermined mapped panel output value TPO, predetermined mapped panel characteristic value TpPn, and flag information corresponding to the previous data Pn&#x2212;1 and current data Pn from a table memory unit that stores predetermined mapped panel output values TPOs, predetermined mapped panel characteristic values TpPns, and flag information corresponding to the predetermined mapped panel characteristic values TpPns, and decodes the read information. The acceleration unit performs interpolations on the decoded mapped panel output value TPO and mapped panel characteristic value TpPn according to the flag information, and generates liquid crystal panel data PO to be output to a liquid crystal panel and previous data of a next frame pPn to be output to the frame memory unit. Thus, the response time accelerator and method make it possible to improve the response time of the liquid crystal even with respect to image data with extremely large or small gray level value.

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Seoul, South Korea

Yong-joon Jung