Samsung Electronics Co., Ltd.

Yong-Jin Yoon

Uk-Rae Cho

Nam-seog Kim

Nam-Seog Kim

Kwang-Jin Lee

Uk-rae Cho

Min-Su Kim

Jong-Cheol Lee

Jung-Woo Park

Tae-Hyoung Kim

Ji-Kyum Kim

Seung-Kweon Yang

Young-Jae Son

Ig-Soo Kwon

An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Integrated circuit pulse generators

A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Delay test device and system-on-chip having the same

Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Amplifier circuit having constant output swing range and stable delay time

A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Method and circuit for writing double data rate (DDR) sampled data in a memory device

An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Apparatus for generating internal clock signal

A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode.

Semiconductor memory device capable of generating variable clock signals according to modes of operation

Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor circuit that delays the reference clock signal; a forward delay array for delaying an output clock signal of the delay monitor circuit to generate delay clock signals; a mirror control circuit that receives the delay clock signals and the reference clock signal to detect one delay clock signal synchronized with the reference clock signal among the delay clock signals; a backward delay array that delays the delay clock signal detected by the mirror control circuit to output a synchronous clock signal; a delay circuit that delays an asynchronous clock signal output through the forward delay array; and a clock driving circuit that outputs the delayed asynchronous clock signal as the internal clock signal when the reference clock signal is not synchronized with one of the delay clock signals.

Synchronous mirror delay circuit and semiconductor integrated circuit device having the same

A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

Synchronous mirror delay circuit with adjustable locking range

A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

Circuits and methods for generating internal clock signal of intermediate phase relative to external clock

Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal. Moreover, the first variable resistance device and the second variable resistance device may be external to the pull-up circuit and the pull-up circuit, respectively. The resistances of the first and second variable resistance devices may also be independently controllable as separate potentiometers.

Integrated driver circuits having independently programmable pull-up and

A semiconductor device connected to a bus consisting of a plurality of signal lines, comprises a first pad connected with a discrete resistor corresponding to the impedance of the signal lines, a plurality of second pads respectively connected with the signal lines, a reference voltage generator for generating a reference voltage, a comparator for comparing the voltage on the first pad with the reference voltage to generate a control signal, a code generator for generating a code signal according to the control signal, a current source for supplying the first pad with variable current according to the code signal, and a data driver for driving data signals to the signal lines connected with the second pads according to the code signal. The code signal is used to match the impedance of the data driver with the impedance of the signal lines.

Semiconductor device with automatic impedance adjustment circuit

Sense amplifiers for integrated circuit memory devices including a bipolar transistor voltage gain input buffer and a first effect transistor latch circuit. The bipolar transistor voltage gain input buffer is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals. The field effect transistor latch circuit is responsive to the bipolar transistor voltage gain input buffer, to latch the voltage differential so amplified, and thereby produce a pair of complementary output signals.

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Seoul, South Korea

Yong-Jin Yoon