Intel Corporation

Shenzhen Mindray Bio-medical Electronics Co., Ltd.

Huawei Technologies Co., Limited

Shanghai Allist Pharmaceuticals, Inc.

Shanghai United Imaging Healthcare Co., Ltd.

Fih (hong Kong) Limited

Shenzhen Futaihong Precision Industry Co., Ltd.

Shanghai Yanfeng Jinqiao Automotive Trim Systems Co. Ltd.

Advanced Micro-fabrication Equipment Inc. China

Tsinghua Shenzhen International Graduate School

Advanced Micro-fabrication Equipment Inc, Shanghai

Intel Corportation

Shanghai Allist Pharmaceutical, Inc.

Yong Jiang

Yuanyuan Li

Qinjun Hu

Yi Wu

Jianhui Guo

Jianghong Du

Lei Shen

Jianfeng Liu

Xingen Yu

Jin Qian

Lijun Zou

Qing Ni

Kuilin Clark Chen

Thomas A Tetzlaff

Ruijia Li

Yi Bin Wang

Oscar Nestares

Lei Chen

Bin Yao

Gowri Somanath

Meng Wang

Ravi L Sahita

Jiayin Zhang

Guei-Yuan Lueh

Xiaoyan Bi

Lei Li

Richmond Hicks

Selvakumar Panneer

Jim Santiago Baca

Yong Huang

Dageng Chen

Justin Lipman

Ke Ding

Kalpana Seshadrinathan

Henry Ho

Salmin Sultana

Robert Colby

Yong Cui

Jian Dong

Xiaoyong Pan

YuHuan Huang

Changwon D Rhee

Jia Lv

Yuxiang Xiao

Yi Wang

Feng Zheng

Jin-Feng Gao

Ning Zhou

Gaoding Fu

Xingjun Pi

Xiaogang Kang

Danyu Bi

Zhiyou Du

Xiaodong Qiu

Shaojun Yao

Jiajie Yao

Xiaofang Zhang

Jianrong Zhang

Zhi Gao

Yong Zhang

Junkai Wu

Xiaorui Xu

Mahamood Hussain

Yanjie Pan

Yongxiong Liao

Dongbiao Cheng

Wenpeng Zhao

Linghyi Kong

Pramod Pesara

Lingyi Kong

Cui Tang

Shuangpeng Zhou

Peiqing Jiang

Chengxi Wu

Yashe Liu

Liyang Ling

Cong Liang

Caihong Ma

Mowei Wang

Ru Liang

Lv Jichao

Wang Wanli

Zou Haifeng

Dzinh J Nguyen

Shifeng Chen

Wei Zhao

Hong Xie

Richard William Kemp

Shuhan Zhao

Benzhu Wei

Yonglei Yao

Zhengzan Shi

Changhai Zhang

Jianjian Han

Ronald Hage

Zian Mu

An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.

Adaptive device data correction with increased memory failure handling

Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.

System and method to accelerate reduce operations in graphics processor

An information transmission method and a related device applied to a cloud service system are provided. The cloud service system includes an arbiter, a first switch, and a first server group. The arbiter is connected to the first server group by using the first switch. The method includes: a first server obtains a first identifier of the first server in the first server group. The first server determines, in a first slot, a first time domain location corresponding to the first identifier. The first time domain location is a time domain location at which the first switch receives a first request to be processed by the arbiter, and different identifiers correspond to different time domain locations in the first slot. The first server sends the first request to the first switch based on the first time domain location.

Information transmission method and related device thereof

Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.

Data stored or free space based FIFO buffer

Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Methods and apparatuses for dynamically changing data priority in a cache

Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.

Water purifier

A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (). The processor can also detect an invalid indirect branch instruction from the processor trace information () and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (). Additionally, the processor can block the application from accessing or modifying memory ().

Malware detection in memory

Some embodiments of the present disclosure relate to a displacer for reducing the consumption of a cryogen used in a superconductive magnet device. The displacer may occupy some space within the cryogen storage cavity or limit the cryogen into a relatively small space surrounding a superconductive coil in the cryogen storage cavity. The displacer may also include a displacer cavity that may be vacuum or contain a cryogen or another substance.

Displacer in magnetic resonance imaging system

A mechanism is described for facilitating efficient communication and data processing across clusters of computing machines in a heterogenous computing environment. A method includes detecting a request for processing of data using a programming framework and a programming model; facilitating interfacing between the programming framework and the programming model, wherein interfacing includes merging the programming model into the programming framework, wherein interfacing further includes integrating the programming framework with a distribution framework hosting the programming model; and calling on the distribution framework to schedule processing of a plurality of jobs based on the request.

Facilitating efficient communication and data processing across clusters of computing machines in heterogeneous computing environment

A system and method for refocusing an image including determining a point spread function (PSF) according to region of interest (ROI) and pixel depth, and converting the PSF to a gradient domain including differentiating the PSF to reduce nonzero elements in the PSF. The technique spreads intensity of pixels into a circle of confusion per the differentiated PSF. A shape of an optical system or aperture of the imaging device may be considered.

Image refocusing

A system for sub-pixel disparity estimation is described herein. The system includes memory circuitry to store image data and at least one processor to execute instructions to calculate a first disparity for a set of reference views. The reference views correspond to a first subset of views among a plurality of sub-aperture views represented in the image data. The at least one processor is to refine the first disparity to a second disparity for the reference views. The second disparity has higher precision than the first disparity. The at least one processor is to map the second disparity from the reference views to a second subset of views among the plurality of sub-aperture views different than the first subset of views.

Efficient sub-pixel disparity estimation for all sub-aperture images from densely sampled light field cameras

In one example, a system for real-time three-dimensional (3D) calibration includes a processor detecting mark corners at two-dimensional (2D) coordinates in an image coordinate system of an image of a specified pattern. The processor determines 3D coordinates of the mark corners in a world coordinate system based on the pattern. The 3D coordinates correspond to the 2D coordinates. The processor determines baseline depth values corresponding to original depth values for proper points on a mark plane, based on the 2D coordinates and the 3D coordinates. The processor generates a fitting model based on the baseline depth values.

Real-time three-dimensional camera calibration

A passive intermodulation elimination method, an apparatus, and a base station are disclosed. The method includes: receiving, by a network device, N pieces of backhauled information, where one piece of the backhauled information includes initial phase information of each carrier on one transmit channel, and N is an integer greater than or equal to 1; and eliminating, by the network device, a PIM of a received signal on a receive channel on the network device based on the N pieces of backhauled information.

Passive intermodulation PIM elimination method, apparatus, and base station

Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

Method and apparatus to improve shared memory efficiency

Growing community of inventors

Shanghai, China

Yong Jiang