Electronics and Telecommunications Research Institute

Yong Je Choi

Kyo Il Chung

Hyun Sook Cho

Ho Won Kim

Moo Seop Kim

Ku Young Chang

Do Won Hong

Young Soo Park

Heui Su Ryu

An apparatus and method for hybrid multiplication in GF(2) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m&#xd7;k] matrix Z for performing a partial multiplication of a(x) and b(x), by dividing b(x) by k bits (k&#x2266;&#x250c;m/2&#x2510;), when multiplication of m-bit multiplier a(x) and m-bit multiplicand b(x) is performed from [(m+k&#x2212;1)&#xd7;k] coefficient matrix of a(x) in GF(2); a partial multiplication unit performing the partial multiplication &#x250c;m/k&#x2510;k&#x2212;1 times in units of rows of the matrix Z to calculate an (&#x250c;m/k&#x2510;k&#x2212;1)-th partial multiplication value and a final result value of the multiplication; and a reduction unit receiving the (&#x250c;m/k&#x2510;k&#x2212;1)-th partial multiplication value fed back from the partial multiplication unit and performing reduction of the value in order to obtain a partial multiplication value next to the (&#x250c;m/k&#x2510;k&#x2212;1)-th partial multiplication value.

[object Object]

Disclosed is an RSA cryptographic processing apparatus capable of performing the fast operating function. A modular multiplication operation or a modular exponentiation operation, i.e., an RSA cryptographic operation, is selectively performed according to a control signal inputted, the modular operation of the data of 512 to 1024 bits is iteratively performed by use of 32-bit operating unit, and the data of 512 to 1024 bits is operated by use of a 32-bit operating unit, thereby minimizing the size of the register storing the data and reducing the size of the cryptographic apparatus, and which the intermediate value generated at the operation process is stored in the internal register instead of the memory, thereby minimizing the times of access to the memory.

RSA cryptographic processing apparatus for IC card

Growing community of inventors

Gwangjoo, South Korea

Yong Je Choi