Silicon Works Co., Ltd.

Lx Semicon Co., Ltd.

Yong Hwan Moon

Myung Yu Kim

Do Seok Kim

Hyun Pyo Cho

Sang Ho Kim

Jun Ho Kim

Jae Ryun Shim

Chul Soo Jeong

Hong Jun Yang

Tae Ho Kim

Jeong Ho Park

Yong Woo Kim

Yong Ik Jung

Young Soo Ryu

Jeong Hoon Nam

Jae Wook Yoo

In Seok Kong

Sang Hoon Paik

A technology for transmitting a training signal with a pattern that enables high-speed data transmission in a training process performed before transmission of video data is disclosed. A method of receiving data in a display driving device according to one of the various embodiments of the present disclosure can include receiving a first training signal transmitted from a display processing device; generating a clock signal based on the first training signal; confirming a second training signal transmitted from the display processing device based on the generated clock signal; and confirming data transmitted from the display processing device based on the second training signal.

Method of receiving data in display driving device, method of transmitting data in display processing device, and display device

A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.

Data transmission circuit

The present disclosure discloses a display driving device and a display device including the same, which enable the influence of high voltage noise to be avoided in display panel driving. The display device includes a timing controller configured to transmit a communication signal, which includes a blank pattern and line data, at a horizontal line interval, and a source driver configured to restore the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data. The timing controller may include a configuration packet in the blank pattern and position the configuration packet in an end period of the blank pattern.

Display driving device and display device including the same

Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

Stream clock generator and embedded DisplayPort system including the same

The present disclosure discloses a display driving device and a display device including the same, which allow transmission data to be converted into a completely random code sequence. The display device may scramble transmission data into a pseudo-random binary sequence (PRBS) using a linear feedback shift register (LFSR), and may change a seed value of the LFSR every time the scrambling is performed.

The present disclosure discloses a display driving device and a display device including the same, allowing high-speed data communication to be supported by controlling the length of a data packet. The display device may include a timing controller configured to transmit a communication signal, and a source driver connected to the timing controller through a communication link and configured to receive the communication signal. The source driver may receive the communication signal having a format of preamble data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data may include a header defining a length of a data packet.

The present disclosure discloses a display driving device and a display device including the same, which are capable of restoring a communication abnormal state to a normal state when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a plurality of source drivers. The display device may include a timing controller configured to transmit a communication signal, a first source driver connected to the timing controller through a first communication link and configured to receive the communication signal, and a second source driver connected to the timing controller through a second communication link and configured to receive the communication signal. The first source driver and the second source driver may receive a restore command from the timing controller in a communication abnormal state and perform a configuration mode, in which options for restoring a communication state are set, according to configuration data received after the restore command.

Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Clock recovery system of displays apparatus

Provided are an embedded DisplayPort (eDP) system and a method for controlling a panel self refresh mode. The eDP system enters a panel self refresh (PSR) mode when an image to display is static in a general mode, and a sink device recovers a stream clock for displaying a static image in the PSR mode.

Embedded DisplayPort system and method for controlling panel self refresh mode

Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

Circuit for controlling variation in frequency of clock signal

The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

Circuit and method for preventing false lock and delay locked loop using the same

Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Growing community of inventors

Daejeon, South Korea

Yong Hwan Moon