Skhynix Inc.

Yong Hwan Hong

Byung Ryul Kim

Byung Wook Kim

Jae Young Lee

Dae Il Choi

Tae Ho Lee

Sun Hak Kim

A memory device includes a memory block including a plurality of pages, a peripheral circuit configured to perform a first program operation for storing first page data and a second program operation for storing second page data after the first program operation, a status register configured to store status information, a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller when the first program operation is being performed, and a status register controller configured to store in the status register first failure information indicating whether the first program operation passes, store in the status register validity information indicating whether the first failure information is valid information within a predetermined time period from when the second program operation starts, and provide the external controller with the status information including the first failure information and the validity information.

Memory system for performing cache program operation and operating method thereof

According to an embodiment, a semiconductor memory device includes a plurality of memory blocks including first to m-th guarantee blocks, wherein m is an integer greater than 1; repair logic suitable for generating bad block information by detecting defective memory blocks among the first to m-th guarantee blocks, and determining first to m-th offset values respectively corresponding to the first to m-th guarantee blocks based on the bad block information; and an address decoder suitable for generating a block selection address by reflecting an offset value selected from the first to m-th offset values onto a block address when the block address corresponds to any of the first to m-th guarantee blocks, and by reflecting the m-th offset value onto the block address when the block address corresponds to any of the memory blocks except for the first to m-th guarantee blocks.

Semiconductor memory device and operating method for repairing guarantee blocks

The present technology relates to a memory device. A memory device according to the present technology includes a memory cell array including a backup block and a data block, a data input/output circuit including a plurality of page buffers that buffer data received from a host, a peripheral circuit configured to perform a program operation of storing the data in the data block, and a backup operation controller configured to control the peripheral circuit to perform a reset operation of stopping the program operation and a backup program operation of storing the data in the backup block when a backup command indicating occurrence of a sudden power off is received from an external controller during the program operation, and the reset operation is an operation of maintaining a state in which the data is buffered in the plurality of page buffers and resetting the peripheral circuit.

Memory system and method of operating the memory system

A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation command.

Memory device with temperature information controller and operating method of the memory device

A memory system includes: a plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller through a channel; a super block including pages included in the planes of at least two memory devices among the plurality of memory devices; and the memory controller for transmitting, to the memory devices, at least one command instructing an operation on the super block and an address corresponding to the command. Each of the memory devices includes: peripheral circuit for performing the operation on the memory cell array; a group selection signal generator for outputting a group selection signal indicating the at least two memory devices constituting the super block; and control logic for controlling the peripheral circuit to perform an operation corresponding to the command, based on the group selection signal.

Memory system and method of operating a memory device included in the same

A memory device according to an embodiment includes a plurality of cell strings each including a select transistor and memory cells connected in series, a peripheral circuit configured to apply a verify voltage to the select transistor and perform an internal operation on the memory cells, and control logic configured to control the peripheral circuit to apply an operation voltage for the internal operation. The control logic includes a bad string management component configured to verify threshold voltages of the select transistor and control the peripheral circuit to perform the internal operation on a cell string including a select transistor passed in verification according to a verify result of the select transistor.

Memory device and method of operating the same

Provided herein is a memory device and a method of operating the same. The memory device may include a CAM block configured to store CAM data required for various operations, a page buffer group configured to store the CAM data read from the CAM block through a CAM read operation, an extra register configured to store extra data generated by performing an operation on the CAM data, an operation logic configured to perform an operation of checking a defect in the extra register, registers configured to sequentially store operation data generated through the defect check operation, a fixed register configured to store fixed data obtained through an operation performed to check an error in the CAM data, and core circuits configured to perform the CAM read operation and transmit the operation data and the CAM data to the extra register, the registers, and the fixed register.

Provided herein may be a priority determination circuit and a method of operating the priority determination circuit. The priority determination circuit may receive request signals from a plurality of microcontrollers respectively corresponding to the plurality of planes, and output response signals corresponding to the request signals depending on a determined priority.

Priority determination circuit and method of operating the priority determination circuit for preventing overlapping operation

The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.

Memory device, memory system including memory device, and method of operating memory system

A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.

Semiconductor memory device and operating method

The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.

Memory device and memory system having the same

Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.

Fail bit counter and semiconductor memory device having the same

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.

Semiconductor memory device and method for program operation having program loops by step voltage

There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed.

Storage device, memory system having the same, and operating method thereof

A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.

Growing community of inventors

Gyeonggi-do, South Korea

Yong Hwan Hong