Samsung Electronics Co., Ltd.

Yong-Hun Kim

Ki-Cheol Lee

Kwang-Hyun La

Sung-Bong Kang

Byoung-Ju Choi

Joo-Young Seo

Ah-Young Sung

Hyungtae Kim

Jin-Soo Park

Seong-soo Lee

Young-Ju Kim

Junho Song

Donghan Lee

Soojin Park

Chang-Sik Yoo

Jin-han Kim

Hyun-Sang Park

Heung-bae Lee

Hyunsang Park

Jae-bum Lee

Hee-Seok Han

Su-Yeon Doo

Hajun Lee

KeeMoon Chun

Dong-Seok Kang

Hye-Jung Kwon

Jae-Bum Lee

Wan-jung Kim

Kyungchun Kim

SeongJong Yoo

Yeonwoo Jung

EunJong Jang

Myoungsik Suh

A column driver integrated circuit (IC) which drives a first group of pixel lines connected to a first group of pixels included in a display panel, and a second group of pixel lines connected to a second group of pixels included in the display panel, the column driver IC including: a master gray scale voltage generation circuit configured to divide a reference voltage to generate tap voltages, and to generate a first low-power mode gray scale voltage based on at least one of the tap voltages; and a first low-power mode amplifier configured to drive the first group of pixel lines based on the first low-power mode gray scale voltage.

Column driver integrated circuit for low-power driving and devices including the same

A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

Memory device including detection clock pattern generator for generating detection clock output signal including random data pattern

A digital-to-analog converter includes an amplifier including at least two input terminals corresponding to a non-inverting input terminal; and a chopping unit performing a chopping operation between voltages provided to the at least two input terminals corresponding to the non-inverting input terminal. The digital-to-analog converter has an X+Y bit structure and removes an offset by performing an interpolation chopping operation and/or a main buffer chopping operation at the same time. The digital-to-analog structure can be embodied in a small area and can process high bit image data.

Digital-to-analog converter

A display driving device includes a timing controller, a power management integrated circuit, and a column driver. The timing controller generates image data including a plurality of pixel data, and generates a power saving signal based on magnitudes of the plurality of pixel data included in the image data. The power management integrated circuit generates a drive voltage having a voltage level that is varied based on the power saving signal. The column driver receives the image data generated by the timing controller, and generates a plurality of output voltages corresponding to the plurality of pixel data included in the image data based on the drive voltage.

Display driving device and display device having the same

A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as 'DMS') blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

Source driver and operating method thereof for controlling output timing of a data signal

A power-on reset circuit includes a voltage detector unit to output an electrical signal in response to a power supply voltage received from a power supply terminal, an inverter to output a reset signal according to a level of the electrical signal from the voltage detector unit, a first switch unit to be turned on or off in response to the reset signal from the inverter; a first discharge unit to discharge the electrical signal in response to the power supply voltage from the first switch unit, a second switch unit to be turned on according to a start pulse signal from an external device and to receive the power supply voltage from the power supply terminal, and a second discharge unit to discharge the electrical signal in response to the power supply voltage from the second switch.

Power-on reset circuit and display device using power-on reset circuit

A gamma voltage generating circuit includes a gamma voltage distribution unit configured to divide a reference voltage to generate a plurality of initial gamma reference voltages, and a gamma voltage selection unit configured to generate gamma reference voltages by selecting first gamma reference voltages, corresponding to a first color pixel, from among the plurality of initial gamma reference voltages and second gamma reference voltages, corresponding to a second color pixel, from among the plurality of initial gamma reference voltages. Herein, an output part of initial gamma reference voltages selected in common as the first and second gamma reference voltages is shared with input parts of the first and second gamma reference voltages.

Gamma voltage generating circuit and display device including the same

A light-emitting-diode driving circuit includes a current driving circuit configured to control current signals flowing through light-emitting-diode strings in response to a first signal that includes information of a light-emitting-diode current, a dynamic headroom controller configured to generate a third control signal that changes according to a change of the current signals flowing through the light-emitting-diode strings based on voltage signals of first terminals of each of the light-emitting-diode strings and a second control signal that includes the information of the light-emitting-diode current, and a power supply circuit configured to generate a light-emitting-diode driving voltage that changes in response to the third control signal, and provide the light-emitting-diode driving voltage to second terminals of each of the light-emitting-diode strings.

Circuit and method of driving light emitting diodes, and light emitting diode system having the same

Provided is an apparatus and method for automatically extracting an interface of embedded software. The method defines an interface of embedded software as a test item for test of the interface of the embedded software, and generates an interface symbol corresponding to the defined test item. The location of the interface symbol is determined, and a test case is generated based on the interface symbol and its location in the software. Embodiments of the invention thus facilitate the testing of software at interfaces between layers in the software.

Apparatus and method for automatically extracting interface of embedded software

A level shifter includes a first input circuit, a first load circuit, a second input circuit, and a second load circuit. The first input circuit receives a first input signal and a second input signal that swing between a first high power voltage and a first low power voltage. The first load circuit generates a high voltage, a sub-high voltage, a low voltage, and a sub-low voltage. The second input circuit receives a first voltage pair including the high voltage and the low voltage, and a second voltage pair including the sub-high voltage and the sub-low voltage. The second load circuit generates an output signal that swings between a second high power voltage and a second low power voltage.

Level shifter

Embodiments of the invention provide a device and a method for automatically testing embedded software, and more specifically for testing interfaces between layers of the embedded software. In one embodiment, the device includes: an emulator; a server including embedded software; an evaluation board configured to download the embedded software from the server and controlled by the emulator; and a host system configured to receive the embedded software from the server and automatically generate test cases for testing the embedded software using the emulator.

Device and method for testing embedded software using emulator

A subharmonic mixer, including an amplification unit for amplifying an input signal using at least one pair of amplification devices connected in parallel and a mixing unit for mixing the amplified signal with local oscillation signals from local oscillators is provided. The mixing unit performs switching over the amplification devices and at least four pairs of switching devices connected in parallel with each other, two pairs of switching devices being connected in parallel with each other and performing switching over one amplification device. The switching devices are supplied with local oscillation signals having different phases respectively, and two switching devices forming a pair are connected in parallel with each other and supplied with local oscillation signals having a 180&#xb0; phase difference therebetween. Accordingly, the switching stage is formed with one stage, the operation is enabled with low-voltage power supplies, and noise performance, linearity, and gain are enhanced.

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Seoul, South Korea

Yong-Hun Kim