Samsung Electronics Co., Ltd.

Yong-Hoon Son

Jong-Wook Lee

Si-Young Choi

In-Soo Jung

Jong-Hyuk Kang

Byeong-Chan Lee

Deok-Hyung Lee

Kihyun Hwang

Yu-Gyun Shin

Jae Hoon Kim

Kwang-Ho Park

Jung Ho Kim

Pil-Kyu Kang

Myoungbum Lee

Seungjae Jung

Yeon-Sil Sohn

Daehyun Jang

Jin-I Lee

Dongwoo Kim

Jongwook Lee

Hyunji Song

Sunghae Lee

Ju-Eun Kim

Sangryol Yang

Gyeonghee Lee

Kyung-Hyun Kim

Kyunghyun Kim

Phil Ouk Nam

JinGyun Kim

Phil-Ouk Nam

Young-Eun Lee

Seungjae Baik

Seung Jae Jung

Won-Bong Jung

Kwangchul Park

Sung-Kwan Kang

Byeongju Kim

Wonbong Jung

Hyung Joon Kim

Jung-ho Kim

Cheol Kyu Kim

Hyun Jung Lee

Hanmei Choi

Woojin Jung

Sun-Ghil Lee

Jin-Hyuk Yoo

Yoonjae Kim

Kwang-Chul Park

Seungwoo Choi

Taek-Jung Kim

JongHeun Lim

Daelok Bae

Byeong-Ju Kim

Jong-Min Lee

Sung-Min Kim

Kohji Kanamori

Eun-Young Lee

Dong-Won Kim

Han-Mei Choi

Young-Woo Park

Jihoon Park

Jun-ho Lee

Jae-young Ahn

Chang-seok Kang

Jaehun Jeong

Joongshik Shin

Jae-Duk Lee

Kyoung-hwan Yeo

Jong-Ryeol Yoo

Joon Sung Kim

Euntaek Jung

Jong-Heun Lim

Vladimir Urazaev

Jin Ha Jeong

Jong-won Kim

Jin-Ha Jeong

Ki Hyun Hwang

Chaeho Kim

Yong-Won Cha

Suk Kang Sung

Yugyun Shin

Sung-Soo Ahn

Sungkwan Kang

Hanvit Yang

Sung-Woo Hyun

Cha-Dong Yeo

Sungwoo Hyun

Kwang Chul Park

Seung Jae Baik

Kihun Hwang

Jongho Woo

InSoo Jung

Junho Cha

Myoung Bum Lee

Gil Sung Lee

Minhyuk Kim

Jae Ho Min

Jin-l Lee

A three-dimensional semiconductor device may include a substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes, a source structure, and a mold structure between the substrate and the stack structure. First vertical channel structures are on the cell array region in vertical channel holes. Each of the first vertical channel structures may include a first barrier pattern, a data storage pattern, and a vertical semiconductor pattern, which are sequentially layered on an inner side surface of one of the vertical channel holes. The mold structure may include a first buffer insulating layer, a first semiconductor layer, a second buffer insulating layer, and a second semiconductor layer sequentially stacked on the substrate. The source structure may be in physical contact with a portion of a side surface of the vertical semiconductor pattern.

Three-dimensional semiconductor memory device and electronic system including the same

A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

Semiconductor memory device, method for fabricating the same and electronic system including the same

A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

Method for forming a three-dimensional semiconductor memory device with an improved etching step

A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Semiconductor memory device including capacitor with a dielectric film on an upper plate region, a lower plate region, and a side surface of a connecting region therebetween

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

Semiconductor memory device

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

Semiconductor memory devices and methods of fabricating the same

A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.

Semiconductor memory devices including stacked transistors and methods of fabricating the same

Three-dimensional semiconductor memory device with concave convex separation structures

A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

Semiconductor memory device and method of manufacturing the same

Disclosed are semiconductor memory devices and methods of fabricating the same. The method including forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that a vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed to, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed may be provided.

Semiconductor memory device and method of fabricating the same

Growing community of inventors

Yongin-si, South Korea

Yong-Hoon Son