Samsung Electronics Co., Ltd.

Yong-Ho Jeon

Bo-un Yoon

Do-hyoung Kim

Dohyoung Kim

Jinwook Lee

Kyoung-hwan Yeo

Sang-Jine Park

Keun-Hee Bai

Kee-Sang Kwon

Kwang-Yong Yang

GeumJung Seong

Sungwoo Myung

Jisoo Oh

Seung-Jae Lee

Myeong-Cheol Kim

Cheol Kyu Kim

Sang-Bom Kang

Sung-il Park

Kye-Hyun Baek

Jae-hyun Park

Hyunwoo Choi

Jung-Chan Lee

Hyung-suk Lee

Yun-il Lee

Dae-young Kwak

Se-Koo Kang

Miri Joung

Sang Hyun Lee

Dong-hyun Kim

Sang-Su Kim

Gi-Gwan Park

Yong-Suk Tak

Cheol Jin Kim

Kyoung-Sub Shin

Jeong Yun Lee

Je-Woo Han

Dae-hyun Jang

Dong Seok Lee

Sun-ki Min

Myung-geun Song

Seung-Seok Ha

Young-ju Park

Kee Sang Kwon

Sung Woo Kang

Keun Hee Bai

An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Integrated circuit device and method of forming the same

Methods of fabricating semiconductor devices comprise forming first active patterns vertically spaced apart on a first active fin of a substrate and second active patterns vertically spaced apart on a second active fin of the substrate that has a first region on which the first active fin is formed and a second region on which the second active fin is formed, forming a first electrode layer on the first and second active fins and the first and second active patterns, forming a first mask pattern overlapping the first electrode layer on the first region, forming a second mask pattern overlapping the first electrode layer on the second region, and using the second mask pattern as an etching mask to etch the first mask pattern and the first electrode layer on the first region to form a first electrode pattern on the second region.

Semiconductor device and method of fabricating the same

A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.

Semiconductor device including self-aligned contact and method of fabricating the semiconductor device

A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Methods of fabricating semiconductor devices

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Semiconductor devices including a dummy gate structure on a fin

A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.

Method of manufacturing semiconductor device to prevent defects

The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

Semiconductor devices

A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

Semiconductor device and method for fabricating the same

Semiconductor devices and methods for fabricating the same

Semiconductor devices and methods of fabricating the same

Growing community of inventors

Hwaseong-si, South Korea

Yong-Ho Jeon