Samsung Electronics Co., Ltd.

Yong-Ho Cho

Ji-Yun Seol

Yeo-Hun Yun

Chan-Hong Kim

Seong-Jin Jang

Min Sagong

Ji-Hoon Lim

Ming Hoka

Ki-Heung Kim

Tae-Yoon Lee

Kyeong-Yeon Kim

Tae-young Kim

Peng Xue

Seung-Joo Maeng

Ho-Young Song

Sung-Nam Hong

Sung-Min Seo

Je-Min Ryu

Neung-Hyung Lee

Jong-Min Oh

Dong-Su Jang

Gil-Su Kim

The present disclosure relates to a communication technique for converging a 5G communication system, which is provided to support a higher data transmission rate beyond a 4G system with an IoT technology, and a system therefor. The present disclosure may be applied to an intelligent service (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail business, security and safety-related service, etc.) on the basis of a 5G communication technology and an IoT-related technology. The present disclosure relates to an efficient method and device for uplink communication in a narrow band system which provides an IoT service in a band for a broadband system, and a method for uplink communication in a narrow band system according to an embodiment of the present disclosure comprises the steps of: receiving, by a terminal, control information associated with uplink transmission of symbols from a base station; and performing, by the terminal, the uplink transmission using symbols except a second symbol overlapping with a first symbol for transmission of an uplink reference signal in a broadband system, on the basis of the control information.

Method and device for communication in narrow band system

The present invention relates to a 5th-generation (5G) or pre-5G communication system, which is to be provided for supporting a higher data transmission rate after the 4th-generation (4G) communication system, such as long term evolution (LTE). The present invention provides a method for receiving a signal in a multi-carrier system, the method comprising the steps of: performing, with respect to an input signal, a waveform pre-processing operation on the basis of at least one of an equalizing operation and a filtering operation; checking whether the waveform pre-processed signal is a Gaussian proximity signal; and performing soft-de-mapping with respect to the waveform pre-processed signal on the basis of a result of the checking.

Apparatus and method for transmitting/receiving signal in multi-carrier system

A method for operating a resource in a base station (BS) in a wireless communication system supporting multi-carrier is disclosed. The method includes acquiring reference information related to at least one resource block (RB) to be allocated to a user equipment (UE), determining a RB type to be used in the at least one RB based on the reference information, and transmitting, to the UE, information related to the RB type to be used in the at least one RB. The present disclosure relates to a communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT), which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology.

Apparatus and method for operating resource in wireless communication system

A method for determining an uplink (UL) channel quality by a base station (BS) includes obtaining a coverage class (CC) value of a user equipment (UE), receiving a random access (RA) signal from the UE, determining an UL channel quality of a band in which the RA signal is transmitted, based on the CC value and the RA signal, and generating UL resource allocation information based on the UL channel quality and transmitting the UL resource allocation information to the UE. The BS includes a transceiver configured to obtain a CC value of a UE and to receive a RA signal from the UE, and a controller configured to determine an UL channel quality of a band in which the RA signal is transmitted, based on the CC value and the RA signal. A UE includes determines a CC value of the UE based on a DL signal.

Method and apparatus for measuring channel in wireless communication system

A method of operating a memory device including a plurality of memory cells may include counting a number of times that the plurality of memory cells during a first time period, comparing the number of times to a reference number, and controlling a refresh interval of a refresh operation for the plurality of memory cells based on a result of the comparison.

Memory device, operating method thereof, and system having the memory device

A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Memory device, method of operating the same, and electronic device having the memory device

A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Level detector, internal voltage generator including level detector, and semiconductor memory device including internal voltage generator

A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved.

Wordline driver, memory device including the same and method of driving a wordline

A semiconductor device includes a comparator, an internal voltage generator, a control signal generator, and a selector. The comparator may compare a reference voltage to an internal voltage and output a comparison signal. The internal voltage generator may generate and output the internal voltage in response to the comparison signal. The control signal generator may generate a control signal. The selector may receive first and second target voltages, and select and output one of the first and second target voltages as the reference voltage in response to the control signal.

Semiconductor device for generating internal voltage and memory system including the semiconductor device

A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.

Semiconductor memory device comprising variable delay circuit

A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

Block decoding circuits of semiconductor memory devices and methods of operating the same

A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal.

Semiconductor memory devices for controlling latency

Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

Method and apparatus for controlling read latency of high-speed DRAM

A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells of the DLL to the output terminal of the DLL.

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Suwon-si, South Korea

Yong-Ho Cho