Samsung Electronics Co., Ltd.

Forhuman Co., Ltd.

Yong-hee Lee

Young-woo Seo

Seung-Ki Chae

Jung-hyun Shin

Young-jo Shin

Sang-gon Lee

In-ju Lee

Kyoung-hye Lee

Jin-ok Jung

Young-hoon Park

Hyun-kuk Shin

Young-pil Kim

Kyu-hyung Kwon

Jong-bok Kim

Won-sik Lee

Hyung-geun Lee

The apparatus for decomposing PFCs includes an external electrode unit which is coupled to a reference voltage and which defines a flow space for the flow of the PFCs, and an internal electrode unit which is located within the flow space of the external electrode unit so as to define a reaction space between the internal electrode unit and the external electrode unit. The apparatus is also equipped with a voltage supply unit which applies an alternating voltage to the internal electrode unit which is of sufficient voltage and frequency to generate an electron beam within the reaction space which is capable of decomposing the PFCs.

Apparatus for decomposing perfluorinated compounds and system for processing perfluorinated compounds using the apparatus

Provided are a communication device having a built-in camera and a system and method of detecting a communication device having a built-in camera. In the system, a communication device can transmit camera existence data or particular identification data thereof, and in response thereto, a detection device can suspend a camera function of the communication device when a user with the communication device enters a security zone. In addition, the detection device can recover the camera function when the user with the communication device exits the security zone.

System and method of detecting communication device having built-in camera

A fixing device for attaching and detaching a dust receptacle to and from a cyclone unit, which comprises a cyclone body and the dust receptacle and mounted in a mounting portion of a cleaner body. The fixing device comprises a dust receptacle comprising a sliding groove formed with a predetermined depth and height extended backward from a center of a bottom side of the dust receptacle that is opposite to a bottom side of the mounting portion. A guide member is disposed in the sliding groove for guiding attachment and detachment of the dust receptacle. An operation lever with a cam part having a cam projection for insertion into the cam guider, is rotated and counter-rotated to thereby move the guide member upward and downward at a height according to an eccentricity of the cam part.

Fixing device for attaching/detaching dust receptacle of cyclone-type vacuum cleaner and vacuum cleaner having the same

In a cyclone dust collecting apparatus for use in a vacuum cleaner, mounted in a dust collecting chamber intercommunicating with a motor driving chamber of a cleaner body, for separating contaminants from an air that is drawn in through a suction brush by a centrifugal force, the cyclone dust collecting apparatus includes: a contaminant receptacle having a contaminant chamber and an air discharge chamber, the contaminant chamber and the air discharge chamber respectively having open upper sides and partitioned from each other; a cyclone unit connected to an upper portion of the contaminant receptacle in a manner of covering the contaminant chamber and the air discharge chamber, the cyclone unit having a hole corresponding to, respectively, an incoming air port through which foreign substance laden air flows in, a centrifuging chamber for separating the foreign substances from the air by a centrifugal effect, a contaminant discharge port through which the separated foreign substances are discharged, an outgoing air port through which cleaned air that is left after separation of the foreign substances is discharged out, and the air discharge chamber; and a duct member connected to the upper portion of the cyclone unit, and having an air inflow channel that is connected to the incoming air port and an air outflow channel that interconnects the outgoing air port with the hole.

Cyclone dust collecting apparatus for use in vacuum cleaner

An integrated circuit device having a first type of pads with a probing portion and a bonding portion. The integrated circuit device includes a memory cell array, a logic circuit, and a plurality of the first type of pads and a plurality of a second type of pads. The second type of pads are electrically connected to the logic circuit. The first type of pads are electrically connected to the memory cell array and the logic circuit. Only the probing portion of the first type of pads is contacted by probes during testing of the memory cell array, and the bonding portion is used exclusively for attachment of a bond wire to permit connection to an external system.

Pad for integrated circuit device which allows for multiple probing and reliable bonding and integrated circuit device including the pad

A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.

Semiconductor device with selectively patterned connection pad layer for

A vertical cavity surface emitting laser (VCSEL) is provided which has a substrate, a first reflector layer formed on the substrate, an active layer formed on the first reflector layer, a second reflector layer formed on the active layer, and an electrode layer formed on the second reflector layer and having a cavity for emitting light from the second reflector layer. Laser light is generated in the active layer between the first and second reflective layers and is emitted through the second reflective layer at the cavity. The first and second reflective layers are each formed of semiconductor material containing impurities, such that the impurities in the first reflective layer are of an opposite type to the impurities in the second reflective layer. The electrode layer has a metal layer having a high electrical conductivity and a conductive auxiliary reflector layer formed between the metal layer and the second reflective layer. The auxiliary reflector layer has a reflectivity which is lower than the reflectivities of either of the first or second reflector layers.

Vertical cavity surface emitting laser

A method is provided for manufacturing a capacitor of a semiconductor device. First, an insulating layer, an etching barrier layer, a first material layer and a second material layer are sequentially stacked on a semiconductor substrate on which a field oxide layer and a gate electrode are formed, and predetermined portions of the stacked layers are sequentially etched to form a contact hole exposing the substrate. Then, a first conductive layer is formed on thge whole surface of the resultant structure having the contact hole. Subsequently, a storage electrode pattern is formed by patterning the first conductive layer and etching the second material layer. Then, a second conductive layer is formed on the whole surface of the resultant structure so as to cover the storage electrode pattern and the first material layer. Thereafter, the second conductive layer is etched to expose the upper surface of the storage electrode pattern. Therefore, the capacitor manufacturing process, particularly, the etching process, is simplified, and can be applied to a capacitor having a COB structure.

Semiconductor device capacitor manufactured by forming stack with

AMOS transistor with enhanced electrical characteristics and a method for manufacturing the same. In the channel region, a first impurity region is provided for adjusting a threshold voltage, a second impurity region is provided which serves as a diffusion barrier, and a third impurity region is provided for preventing a punchthrough. These regions are formed sequentially at subsequently shallower depths in the substrate. The disclosed transistor minimizes short-channel effects and punchthrough without reducing the current driving capability of the device.

Metal oxide semiconductor transistor and a method for manufacturing the

A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.

Method of maufacturing a semiconductor device having a low resistance

A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.

Growing community of inventors

Shiheung, South Korea

Yong-hee Lee