Samsung Electronics Co., Ltd.

Yong-Ha Park

Hyun-suk Kim

Jin-Aeon Lee

Young-jin Chung

Kil-Whan Lee

Yun-Kyoung Kim

A graphic processing unit, a graphic processing system comprising the same, and a rendering method using the same. The graphic processing unit includes a geometry processing unit configured to receive a vertex and to output a primitive and information about texture patches corresponding to the primitive using the vertex, and a rendering processing unit configured to convert the output primitive into a fragment and to perform fragment shading on the converted fragment, wherein the texture patch indexed by the texture patch information is pre-loaded to the rendering processing unit before the fragment shading is performed.

Graphic processing unit for image rendering, graphic processing system including the same and image rendering method using the same

A method of operating a graphic processor unit includes detecting from a program code a code area that instructs a load/store unit to load data stored in a plurality of rows of a memory to registers of a register file using a scheduler; and, using a load/store unit, loading data to the at least one register in response to instructions corresponding to the code area. A second instruction of the instructions instructs the load/store unit to write control information in a control register of the at least one register. The control information includes at least mask bits designating selected rows of the memory that store data to be loaded from the plurality of rows of the memory, a span field representing a relationship of the plurality of rows of the memory to each other and a stride field. A third instruction of the instruction instructs the load/store unit to store the data sequentially from a row of the memory corresponding to an address written in a base register of the register file to a first register of the register file, according to the control information.

Graphic processor unit and method of operating the same

Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Growing community of inventors

Seongnam-si, South Korea

Yong-Ha Park