Samsung Electronics Co., Ltd.

Yong-Gwon Jeong

Jong-Hyun Choi

Kwang-il Park

Ki-Seok Oh

Joon-Young Park

Joung-Yeal Kim

Si-Hong Kim

Yong-cheol Bae

Jung-Yong Lee

Young-Hoon Sohn

Yong-Hun Ahn

Ju-Suk Bang

Chae-Il Lim

A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Semiconductor memory devices, memory systems and refresh methods of the same

An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.

On-die termination circuit, semiconductor memory device and memory system

A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

Semiconductor device capable of testing a transmission line for an impedance calibration code

A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.

Semiconductor device having output buffer initialization circuit and output buffer initialization method

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Uiwang-si, South Korea

Yong-Gwon Jeong