Samsung Electronics Co., Ltd.

Yong-Don Kim

Eung-Kyu Lee

Hoon Suk Chang

Mueng-Ryul Lee

Se-Jin Park

Yong-Chan Kim

Joung-Ho Kim

Dong-Eun Jang

Jong-Hwan Oh

Sung-Ryoul Bae

Seo-In Pak

Soo-Bang Kim

Jong-Wook Lim

A semiconductor device includes at least one gate electrode on a substrate structure, at least one drain region doped with impurities of a first conductivity type, a first well region doped with impurities of the first conductivity type under the at least one drain region, and at least one source region doped with impurities of the first conductivity type. The device also includes a first barrier impurity region and a second barrier impurity region. The first barrier impurity region is doped with impurities of the first conductivity type and electrically insulating upper and lower portions of the substrate structure from each other. The second barrier impurity region is doped with impurities of a second conductivity type. A portion of the second barrier impurity region has an uneven shape and overlaps the at least one drain region.

Semiconductor devices and methods of manufacturing the same

A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias.

Semiconductor device

A semiconductor integrated circuit device and method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.

Semiconductor integrated circuit device and method of fabricating the same

Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second buried impurity layer, which contains impurities of a second conductivity type and of a second concentration, using blank implantation; and forming an epitaxial layer on the substrate having the first and second buried impurity layers, wherein the first concentration is higher than the second concentration.

Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device fabricated using the method

A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

Semiconductor integrated circuit devices

An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

Growing community of inventors

Hwaseong-si, South Korea

Yong-Don Kim