Samsung Electronics Co., Ltd.

Yong-Chun Kim

Hong-Kyu Kim

Seh-Woong Jeong

Kyoung-Mook Lim

Yang-Ho Kim

A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Apparatus for controlling multi-word stack operations using a multi-bank stack in digital data processors

A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.

Data processing apparatus and method for performing different word-length arithmetic operations

A microprocessor with an efficient and powerful coprocessor interface architecture is provided. The microprocessor has a set of generic coprocessor instructions on its instruction map and interface signals dedicated to the coprocessor interface. Depending on which coprocessor is interfaced to the microprocessor, the generic.coprocessor instructions are renamed to the specific coprocessor commands. When a coprocessor instruction for a specific function is fetched and decoded by the host processor, the appropriate command is issued through the coprocessor interface signals to the coprocessor and the coprocessor performs the required tasks. Hence, the coprocessor interfaced with the host processor need not have its own program. The pipelined operations of the coprocessor are synchronized with pipelined operations of the host processor.

Data processing system and method for performing enhanced pipelined operations on instructions for normal and specific functions

Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a &ldquo;1&rdquo; to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n&minus;m) bit component, and a set of D (data) flip-flops for storing outputs of the half-adders. The set of half-adders are divided into two sections, one of which is a first adder section for adding a &ldquo;1&rdquo; to the lower-order m bit component and the other of which is a second adder section for adding a carry signal from the first adder section to the higher-order (n&minus;m) bit component. The set of D flip-flops are divided into two sections, one of which is a first register section to store outputs of the first adder section and the other of which is a second register section to store outputs of the second adder section. The n-bit input signal is comprised of the outputs of the first and second register sections. The novel n-bit binary counter further comprises a clock gating circuit which allows the second register section to store the outputs of the second adder section only when the carry signal of &ldquo;1&rdquo; is generated from the first adder section. Since D flip-flops of the second register section are not toggled until the carry signal of &ldquo;1&rdquo; is generated from the first -adder section.

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Kyunggi-do, South Korea

Yong-Chun Kim