Samsung Electronics Co., Ltd.

Yong Cheol Bae

Joon Young Park

Ki Won Lee

Seung Jun Bae

Young Jin Jeon

Min Su Ahn

David Moon

Young Chul Cho

Yoon Joo Eom

An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

Output driver, devices having the same, and ground termination

A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).

Semiconductor memory device, a memory module including the same, and a memory system including the same

A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means 'output high level voltage.'

A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.

Small signal receiver and integrated circuit including the same

An auto precharge control signal generating circuit includes an output enable circuit that is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal. A delay circuit also is provided which generates a 1 clock delay signal by delaying an active period of a column bank address signal by 1 clock, and generates a 1 clock delay signal having an active period including a non-active period sufficiently between a previous column bank address signal and a present column bank address signal in case that the burst length is 1. A combining circuit generates an auto precharge control signal by combining the column bank address signal and the 1 clock delay signal in response to the output enable signal, in order to perform the auto precharge operation after delaying 2 clock from the last data input in response to a continued auto precharge burst write command. Therefore, when the burst length is 1 in case that the time from the last data input to the auto precharge is 2 clock cycles in burst write, the present invention prevents the generation of unnecessary auto precharge control signal resulting from the crossing of the 1 clock delay signal and the column bank address signal in the middle of continuous burst write operation.

Growing community of inventors

Yongin-si, South Korea

Yong Cheol Bae