Samsung Electronics Co., Ltd.

Yong-Cheol Bae

Sei-seung Yoon

Jung-hwa Lee

Dong-Il Seo

Woo-seop Jeong

Gi-hong Kim

Integrated circuit memory devices include precharge controller circuit, which generates a precharge control signal in response to completion of a write operation on a first input/output bus. A precharge circuit drives the first and a input/output buses to a predetermined voltage level in response to the precharge control signal. Multiple switches may be used to couple the first and second input/output buses to the memory cell array and these switches may also be coupled to a column select line. The switches may be responsive to a column select signal carried on the column select line such that one or more memory cells are coupled to the first input/output bus and one or more memory cells are coupled to the second input/output bus simultaneously. Because both of the input/output buses are coupled to the memory cell array in response to the column select signal, the memory cell array may be susceptible to bit line disturbance in which charges remaining on one input/output bus from a previous write operation corrupt memory cells during a write operation on a second input/output bus. By driving the first and second input/output buses to a predetermined voltage level after completing a write operation on one of the two input/output buses, bit line disturbance may be prevented.

Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations

A semiconductor memory device, in which the output of an internal supply voltage is stable, is provided. The semiconductor memory device includes a memory cell array block, a differential amplifier, using a reference voltage and an internal supply voltage fed back from the memory cell array block as inputs, an internal supply voltage driver for supplying an internal supply voltage to the memory cell array block in response to the output of the differential amplifier, a pull down circuit for pulling down the output port of the differential amplifier in response to a control signal having a predetermined pulse, and a control signal generating circuit for generating the control signal.

Semiconductor memory device having stable internal supply voltage driver

An input and output line equalizing circuit for connection to a pair of input and output lines of a memory device. The equalizing circuit includes an equalization control circuit providing at an output a precharge signal, and an equalizing unit connected to the input and output lines. The equalizing unit responding to receipt of a precharge signal from the equalization control circuit to maintain the pair of input and output lines at the same voltage level. The equalizing control circuit includes a first transmission gate and a second transmission gate.

Memory device and equalizing circuit for memory device

An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.

Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation

A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole. After removal of the masking layer, the etching stopper layer and the second insulator layer are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized by CMP procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the cylindrical storage node having the sidewall spacer and the second polysilicon layer in self-alignment.

Method for fabricating a capacitor for a dynamic random access memory cell

Address decoders receive an address signal and decode the address signal to drive word lines of an integrated circuit memory device. The address decoder includes an address latch that generates an effective address from the address signal. A predecoder generates a predecoded address from the effective address. A main decoder generates from the predetermined address a main address that is applied to the word lines. A first circuit enables the predecoder before the effective address is generated by the address latch. A second circuit may also be provided that resets the effective address after the predecoded address is generated from the effective address. The second circuit may include a circuit that disables the predecoder after the predecoded address is generated from the effective address and a circuit that resets the effective address after the predecoder is disabled.

Reduced delay address decoders and decoding methods for integrated circuit memory devices

Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.

Integrated power supply voltage generators having reduced susceptibility

A semiconductor memory device having a plurality of memory array banks, a plurality of active array voltage generators, a standby array voltage generator and a plurality of switching means is provided. The semiconductor memory device includes a plurality of memory array banks in which information is stored, a plurality of active array voltage generators connected to the memory array banks, for generating predetermined active voltages in response to memory array bank enable signals for activating the memory array banks, a standby array voltage generator for generating a predetermined standby voltage so that the memory array banks are maintained in a standby state for operation, and a plurality of switching means connected between the memory array banks and the standby array voltage generator, for disconnecting the output of the standby array voltage generator from memory array banks in response to memory array bank enable signals for activating the memory array banks. The power consumption of the semiconductor memory device is reduced.

Multi-bank memory devices having common standby voltage generator for

In a semiconductor memory device, a plurality of output buffers, one for each output data bit, are powered by an internal voltage control circuit so as to provide high speed operation yet minimize power consumption. The internal voltage control circuit inclues multiple internal voltage generators. Responsive to the number of output buffers in use during a read operation, one or more of the voltage generators are activated to power the output buffers. Additionally, the current capacity of each of the individual voltage generators is controlled responsive to the number of output buffers in use during the read operation, so that bandwidth of the memory device is maximized but power is not wasted.

Circuit for controlling internal voltage for output buffer of

Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential. To supplement the voltage boosting capability of the main pump, a backup voltage boosting circuit is provided containing an independent voltage level detector and at least one backup pump coupled in series therewith, to drive the signal line to the boosted reference potential, if the potential of the signal line drops below a third reference potential which may be greater than or equal to the second reference potential. Accordingly, the occurrence of relatively small voltage sags in the potential of the boosted signal line (e.g., Vpp) can trigger the backup pump during anticipated high current loading conditions, while the occurrence of larger voltage sags in the potential can trigger the main pump to assist the backup pump.

Voltage boosting circuits having backup voltage boosting capability

A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.

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Seoul, South Korea

Yong-Cheol Bae