Hong Kong Applied Science and Technology Research Institute Company, Limited

Chinese Academy of Sciences

Yong Cai

Baoshun Zhang

Hung Shen Chu

Ka Wah Chan

Guohao Yu

Xiaodong Zhang

Fei Xu

Fu Chen

Hung-Shen Chu

Shengmei Zheng

Wenxin Tang

Yibin Zhang

Zhihua Dong

Li Min Lin

Sheng Mei Zheng

The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.

Ballistic transport semiconductor device based on nano array and manufacturing method

The present invention discloses a wafer-level semiconductor device and a manufacturing method thereof. The wafer-level semiconductor device comprises a wafer-level substrate; a plurality of serial groups formed on a surface of the substrate and are disposed in parallel, each serial group comprising a plurality of parallel groups disposed in series, each parallel groups comprising a plurality of unit cells disposed in parallel, wherein each unit cell is an independent functional unit which is formed by processing a semiconductor layer directly grown on a surface of the substrate; and a lead, which is at least electrically connected between two selected parallel groups in each serial group to make ON-voltages of all the serial groups substantially consistent. The device of the present invention, with a simple structure, a simple and convenient manufacturing process, and a high efficiency to produce qualified products, can be put into large-scale production and application.

Wafer-level semiconductor device and manufacturing method thereof

A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (), a drain electrode (), a main gate (), a top gate (), an insulating dielectric layer () and a heterostructure, wherein the source electrode () and the drain electrode () are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor () and a second semiconductor (); the first semiconductor () is disposed between the source electrode () and drain electrode (); the second semiconductor () is formed on the surface of the first semiconductor () and is provided with a band gap wider than the first semiconductor (); the main gate () is disposed at the side of the surface of the second semiconductor () adjacent to the source electrode (), and is in Schottky contact with the second semiconductor (); the dielectric layer () is disposed on the surfaces of the second semiconductor () and the main gate () and between the source electrode () and the drain electrode (); the top gate () is formed on the surface of the dielectric layer (), at least one side edge of the top gate extends towards the direction of the source electrode () or the drain electrode (), and the orthographic projection of the top gate overlaps with the two side edges of the main gate (). When the HEMT device is at work, the main gate () and the top gate () are respectively controlled by a control signal. The device can effectively inhibit the 'current collapse effect'.

Group III nitride high electron mobility transistor (HEMT) device

The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness of the polishing stop points material being larger than hardness of the surface material. Therefore, the present method can achieve super flat polishing surface without removing polishing stop points.

Method of super flat chemical mechanical polishing technology and semiconductor elements produced thereof

The present invention provides a method of fabricating vertical LED structures in which the substrate used for epitaxial layer growth is removed through polishing. The polishing technique used in an exemplary embodiment is chemical mechanical polishing using polish stops to provide a sufficiently level plane. Polish stops are provided in the multilayer structure before polishing the surface, the hardness of the polish stop material being greater than the hardness of the material that needs to be removed. Consequently, vertical LEDs can be produced at a lower cost and higher yield compared to either laser lift-off or conventional polishing. Exemplary vertical LEDs are GaN LEDs. The polish stops may be removed by saw dicing, laser dicing or plasma etching.

Optimization of polishing stop design

A method of making a thin gallium-nitride (GaN)-based semiconductor structure is provided. According to one embodiment of the invention, the method includes the steps of providing a substrate; sequentially forming one or more semiconductor layers on the substrate; etching a pattern in the one or more semiconductor layers; depositing a dielectrics layer; forming a photoresist on a portion of the dielectrics layer, wherein the portion of the dielectrics layer is deposited on the one or more semiconductor layers; depositing a primer; removing the photoresist layer, wherein the primer on the photoresist is also removed; depositing a superhard material, wherein the superhard material forms in the pattern; and removing the substrate. Accordingly, the superhard material may be selectively deposited in only areas where the superhard material is desired. Vertical GaN-based light emitting devices may then be formed by cutting the semiconductor structure.

Method of producing thin semiconductor structures

A vertical gallium-nitrate-based LED and method of making a vertical gallium-nitrate-based LED using a stop layer is provided. Embodiments of the present invention use mechanical thinning and a plurality of superhard stop points to remove epitaxial layers with a high level of certainty. According one embodiment, the method of making a vertical LED includes forming a plurality of layers on a sapphire substrate, forming a plurality of stop points in the plurality of layers, removing the sapphire substrate and part of a u-GaN layer using mechanical thinning, wherein the mechanical thinning stops at an end of the plurality of stop points, selectively etching the u-GaN layer and exposing at least a part of the highly doped stop layer, and forming an n-electrode on the highly doped stop layer.

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Suzhou, China

Yong Cai