Korea Electronics Technology Institute

Other

Korea Institute of Industrial Technology

Yong-Bae Dhong

Min-su Jeong

Jin-Tae Kim

Yong-Soo Cho

Soo-Won Kim

Jin-Woong Cho

Hyung-gi Kim

Jong-Ho Paik

Kwang-Ho Choi

Sarm-Goo Cho

Kee-Tag Lim

Soo-won Kim

Hyoung-Kyu Song

Disclosed is a method of estimating carrier frequency offset in an OFDM system. The method includes the steps of forming one OFDM symbol which has M repeated identical signal block, being a base sub-block; forming a 2 number of identical ith sub-blocks using an M/2 number of the M number of base sub-blocks as a unit; and estimating an ith carrier frequency offset &egr; using a correlation between two adjacent ith sub-blocks in the 8 number of the ith sub-blocks.

Method of estimating carrier frequency offset in an orthogonal frequency division multiplexing system

Disclosed is a DPLL circuit including a PCR register receiving and storing PCR values; an LPCR counter counted by a system clock; an LPCR register fetching an LPCR value every PCR input cycle; a phase error detector determining a difference in values stored in the PCR and LPCR registers, and calculating a present phase error requiring compensation; an interpolator interpolating signals between phase error values; a gain calculator determining a difference between consecutive LPCR values, then calculating a gain value, a D/A converting portion multiplying values output from the interpolator and the gain calculator, then converting the resulting signals into analog signals; and a VCO generating system clock frequencies according to signal voltage output from the D/A converting portion. In another aspect, the DPLL circuit is used in MPEG2 systems. Here, the PCR register receives and stores PCR values, and the LPCR register fetches LPCR values, the PCR and LPCR values including a 9-bit extension and a 33-bit base, the base increasing by 1 every time the extension becomes 300. Further, the VCO generates frequencies in a predetermined range from 27 MHz according to signal voltage output from the D/A converting portion, and an STC circuit adds the difference in values between the PCR and the LPCR values to the LPCR base value, then outputs the resulting value.

Digital phase locked loop circuit for PCR recovery

A resolution enhancement apparatus and method of a laser printer using a modulated laser beam is adapted to an image forming apparatus of the laser printer, and includes a memory for storing sequentially input image data in a sequential scanning method, rearranging a scanning line order and generating an M.times.M sample window, M being an integer, a first processor for producing (M-2).sup.2 3.times.3 sample windows using the M.times.M sample window, determining which mask pattern among a plurality of mask patterns is coincident with each of the produced 3.times.3 sample windows, and outputting predetermined data with respect to direction and density of the image data according to the mask pattern, a second processor for determining to which group among a plurality of groups the image data belongs by using the predetermined data output from the first processor, and altering the image data into predetermined image data corresponding to the group to output the altered data, and a signal modulator for modulating the data output from said second processor into a predetermined pattern and outputting the modulated pattern, thereby minimizing the use of memory space by using four row line memories and enhancing resolution by expressing finite shapes according to nineteen modulation patterns while eliminating the more severe portions of pixel magnitude variation (step phenomenon).

Method and apparatus for enhancing laser printer resolution by using a

A resolution enhancement apparatus and method of a laser printer using a modulated laser beam is adapted to an image forming apparatus of the laser printer. It includes a memory for storing sequentially input image data in a sequential scanning method, rearranging a scanning line order and generating a 5.times.5 sample window. Also included are a first processor for classifying and outputting a pattern of the image data according to bitmap information in a pixel using nine 3.times.3 masks produced from the 5.times.5 sample window supplied from the memory, a second processor for using pixel density to classify data output from the first processor into a plurality of groups and outputting data of the classified groups, and a signal modulator for modulating data output from the second processor into a predetermined pattern and outputting the modulated pattern. This minimizes the use of memory space by using four row line memories and enhancing resolution by expressing finite shapes according to nineteen modulation patterns while eliminating the more severe portions of pixel magnitude variation (step phenomenon).

Method and apparatus for enhancing laser printer resolution

Growing community of inventors

Kyungki-do, South Korea

Yong-Bae Dhong