Apple Inc.

Ramot at Tel-aviv University Ltd.

Yonathan Tate

Tomer Ish-Shalom

Moti Teitel

Nir Tishbi

Asaf Landau

Roy Roth

Naftali Sommer

Eli Yazovitsky

Michael Tsohar

Eyal Gurgi

Micha Anholt

Dan Raphaeli

Barak Baum

Ilia Benkovitch

Or Levi

Ruby Mizrahi

Michael Jeffet

Amit Pinchas Aylon

Armand Chocron

A controller includes an interface and a processor. The interface communicates with memory cells. The processor reads a Code Word (CW) from the memory cells using read thresholds to produce respective readouts, the read thresholds defining zones, identifies a subgroup of the memory cells associated with zones positioned about a Read Voltage (RV) predetermined between adjacent first and second Programming Voltages (PVs), estimates for each zone, based on the readouts, first and second cumulative counts of the memory cells corresponding to the first and second PVs, models first and second PDFs associated respectively with the memory cells programmed to the first and second PVs, based on the first and second cumulative counts, calculates for the zones respective reliability measures, based on the first and second PDFs, and assigns the reliability measures to bits of the CW, and decodes the CW by applying soft decoding to the assigned reliability measures.

Efficient estimation of threshold voltage distributions in a nonvolatile memory

A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

Readout from memory cells subjected to perturbations in threshold voltage distributions

A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

Scheduling of iterative decoding depending on soft inputs

A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

Calculating soft metrics depending on threshold voltages of memory cells in multiple neighbor word lines

A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

Positioning read thresholds in a nonvolatile memory based on successful decoding

A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

Overcoming saturated syndrome condition in estimating number of readout errors

A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np&#xb7;NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.

Performance in reading memory cells affected by neighboring memory cells

An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

Iterative decoding with early termination criterion that permits errors in redundancy part

A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

Efficient LDPC decoding with predefined iteration-dependent scheduling scheme

A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.

Syndrome weight based evaluation of memory cells performance using multiple sense operations

A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vectoris produced by multiplying the data vector by a data sub-matrix Hof the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vectorbased on a decomposition of a parity sub-matrix Hof the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as H, C is matrix that is smaller than H, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation H=A+UCV.

Data encoding by efficient inversion of a parity-check sub-matrix

A decoder includes one or more Variable-Node Processors (VNPs) that hold respective variables, and logic circuitry. The logic circuitry is configured to decode a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations such that each iteration involves processing of at least some of the variables, to hold one or more auxiliary equations derived from the check equations, so that a number of the auxiliary equations is smaller than a number of the check equations, to evaluate the auxiliary equations, during the sequence of iterations, using the variables, and, in response to detecting that the variables satisfy the auxiliary equations, to terminate the sequence of iterations and output the variables as the decoded code word.

Efficient convergence in iterative decoding

A technique of mapping data, suitable for Peak to Average Power Ratio (PAPR) reduction while transmitting data portions via a communication channel limited by a peak power p. The mapping is performed by utilizing a Markovian symbol transition probability distribution with quantized probabilities and by selecting, for a specific data portion at a current channel state, such a binary symbol (called thinned label) which allows puncturing one or more bits in the thinned label's bit sequence before transmission.

Technique for PAPR reduction in communication channel

A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

On-the-fly evaluation of the number of errors corrected in iterative ECC decoding

A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.

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Kfar Saba, Israel

Yonathan Tate