Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Yonatan Tzafrir

Mordekhay Zehavi

Mahmud Asfur

Eyal Widder

Hannon Aharon Borukhov

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.

Dynamic calibration of frequency and power storage interface

A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Interface adjustment processes for a data storage device

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

Method for maximizing frequency while checking data integrity on a physical interface bus

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

Method for maximizing power efficiency in memory interface block

A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.

Systems and methods of adjusting an interface bus speed

A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.

Memory system and method for adaptive auto-sleep and background operations

A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.

Data storage based upon temperature considerations

Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.

Growing community of inventors

Petah Tikva, Israel

Yonatan Tzafrir