Freescale Semiconductor,inc.

Yonatan Naor

Guy Drory

Aviel Livay

Yuval Neeman

Ron Bercovich

Dror Gilad

Yosef Kazaz

Gilad Dror

Ron Berkovich

A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element from an odd memory unit of a pair of memory banks and fetches a second information element from an even memory unit of the pair of memory banks; wherein the first and second information elements are two consecutive interleaved address information elements.

Contention free parallel access system and a method for contention free parallel access to a group of memory banks

A method and a device having interleaving capabilities, the device comprises a first interleaver; the first interleaver comprises a first register, a second register, a first adder and a second adder; wherein the first register is coupled to the first adder and to the second adder; wherein the second register is coupled to the second adder; wherein the first adder is adapted to add a current first register value to a first coefficient to provide a next first register value that is stored at the first register; wherein the second adder is adapted to add a current first register value to a second coefficient, to a third coefficient and to a current second register value to provide an interleaved output value.

Device having interleaving capabilities and a method for applying an interleaving function

A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.

Device having turbo decoding capabilities and a method for turbo decoding

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Herzelia, Israel

Yonatan Naor