Magnachip Semiconductor, Inc.

Sk Keyfoundry Inc.

Key Foundry Co., Ltd

Yon Sup Pang

Francois Hebert

Seong Min Cho

Ju Ho Kim

Tae Hoon Lee

Hyun Kwang Shin

Yu Shin Ryu

Hyun Chul Kim

Young Ju Kim

A semiconductor device including: a semiconductor substrate including a buried layer; and a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate, wherein the deep trench isolation includes: a first point disposed near the upper surface of the semiconductor substrate; a second point disposed near the buried layer; and a third point disposed near a bottom face of the deep trench isolation, and wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point, is disclosed.

Bipolar-CMOS-DMOS semiconductor device having a deep trench isolation structure for high isolation breakdown voltage

A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.

Semiconductor device with increased isolation breakdown voltage

A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.

Semiconductor device comprising Schottky barrier diodes

Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Low-cost semiconductor device manufacturing method

The present examples relate to a Schottky diode having floating guard rings and an additional element isolation layer configured to further improve a breakdown voltage of the Schottky diode, while maintaining the turn-on voltage and current in the forward characteristic, compared to a related Schottky diode. The floating guard rings in the examples are located in a position between the anode and the cathode regions or under the anode.

Schottky diode having floating guard rings

The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.

Vertical bipolar junction transistor and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well region disposed in a substrate, a gate disposed on the substrate, a halo region disposed in a channel region under the gate, and a source LDD region and a drain LDD region disposed on opposite sides of the halo region.

Growing community of inventors

Cheonan-si, South Korea

Yon Sup Pang