Microchip Technology Inc.

Quinstar Technology, Inc.

Yon-Lin Kok

Pei-Ming Daniel Chow

Steven Schell

Jing Zhu

A Class-F power amplifier includes a harmonic matching network topology comprised of circuit elements configured relative to an output network of the power amplifier. The harmonic matching network topology suppresses higher-order harmonics in such a power amplifier and includes coupled-line capacitors and open-stubs that introduce harmonic terminations in the output network, and quarter-wavelength transmission lines to match an overall network to a 50-ohm output load. The harmonic matching network topology enables the power amplifier to exhibit desired performance characteristics in specific frequency ranges for high-power applications.

Harmonic matching network for increasing performance in class-F power amplifiers

A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.

Compact electrostatic discharge (ESD) protection structure

A microwave radio frequency (RF) front end module (FEM) having a low noise amplifier (LNA) with a bypass mode uses a single-pole-triple-throw RF switch that reduces insertion loss to about 1 dB and thereby improves RF receiver sensitivity over existing technology two series connected single-pole-double throw RF switches. The single-pole-triple-throw RF switch may be three metal oxide semiconductor field effect transistor (MOSFET) RF switches that may be arranged with a common source input and isolated independent drain outputs. The RF switches may be single, double or triple gate MOSFET RF switches. The MOSFET RF switches may also be configured as complementary metal oxide semiconductor (CMOS) field effect transistor (FET) RF switches.

Reducing insertion loss in LNA bypass mode by using a single-pole-triple-throw switch in a RF front end module

A single pole double throw (SPDT) switch is fabricated on an integrated circuit (IC) and may comprise two radio frequency (RF) switching devices each having a separate DC blocking capacitor coupled between respective RF switching devices and a common node. A DC connection is provided between the two RF switching devices with a thin electrically conductive line. This thin electrically conductive line provides for increased isolation between the two RF switching devices and decreased insertion loss. The increased isolation and/or decreased insertion loss is accomplished by tuning the thin electrically conductive line through the characteristic impedance of the line when impedance matching conditions are met. Undesired circuit resonance(s) in the SPDT switch may be substantially reduced by using two or more thin electrically conductive lines that further reduce the thin electrically line(s) inductance.

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Cerritos, CA, United States of America

Yon-Lin Kok