Sun Microsystems, Inc.

Oracle America, Inc.

Fujitsu Corporation

Other

Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Hal Computer Systems, Inc.

Montalvo Systems, Inc.

Yolin Lih

Dennis L Wendell

Jun Liu

Ajay Bhatia

Daniel Fung

Shyam Sundar Balasubramanian

Mercedes E Gil

Norman C Chou

Chih-Wei David Chang

Leon Kuo-Liang Peng

William Warren Walker

Richard L Schober, Jr

Prasad Vajjhala

Rick Reeve

Dev Datta

Mohamed Magdy Talaat

Hung Jen (Henry) Wu

Shyam Balasubramanian

A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states.

Enhanced signaling sensitivity using multiple references

A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Memory device with split power switch

An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

Elastic power for read margin

An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

Elastic power for read and write margins

Various implementations are provided that may be used to improve the writeability of individual memory cells providing internal power switching. For example, in one implementation, a method is provided for operating a memory device including a first static random access memory (SRAM) cell including first and second cross-coupled logic gates. The method includes providing a first power level to the first and second cross-coupled logic gates during a read operation performed on the first SRAM cell, and receiving a logic signal at the first SRAM cell. The method also includes switching within the first SRAM cell from providing the first power level to the cross-coupled logic gates to providing a second power level to the cross-coupled logic gates in response to the logic signal to facilitate writing a first logic state into the first SRAM cell.

Method of operating memory cell providing internal power switching

A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load device, each biased by a bias voltage from the bias circuit; and (c) a third input device and a fourth input device that are connected in series with the first load device and the second load device, respectively. In that differential amplifier, the differential input signal is applied across the first and second input devices, as well as across the third and the fourth input devices. The first, second, third and fourth input devices are sized such that a total current in the first and second input devices bears a predetermined ratio to a total current in the third and fourth input devices.

Symmetrical differential amplifier

A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the identification component at the destination interconnect device. The identification component is then processed at the destination interconnect device, the identification component relating to the contents of the data. The invention extends to a machine-readable medium embodying a set of instructions for executing the method and to an interconnect device.

Method and system to control the communication of data between a plurality of interconnect devices

Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.

Keeper circuits having dynamic leakage compensation

A method and system to arbitrate between a plurality of resource requests are disclosed. In each arbitration within a current round of arbitration, a winning request is identified based on a priority associated with each requester participating in the arbitration and a set of values stored in a mask register. In response to identifying the winning request, a mask register value corresponding to a requestor of the winning request is updated to disqualify this requestor from further participation in the current round of arbitration. When the current round of arbitration completes, the set of values in the mask register is reset to allow each requestor to participate in the next round of arbitration. The current round of arbitration begins when each requester is qualified to participate in the current round of arbitration and completes when every participating requestor has been disqualified.

Mask-based round robin arbitration

A method and system to arbitrate requests of a plurality of ports of an interconnect device are provided. Every port receives combined pending request data that includes a pending request indicator associated with each of the plurality of ports. Each pending request indicator specifies whether a corresponding port has a pending request that needs to be submitted to a request bus of the interconnect device. Further, at each port, a turn to submit a request to the request bus is allocated to one of the plurality of ports based on the combined pending request data, a set of values stored in a mask register and a priority scheme associated with the plurality of ports.

Request bus arbitration

A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address then these entries are invalidated. If a search of the translation table is required then the method involves the retrieval from the translation table, and insertion into the TLB, of a translation for the specified input address and possibly one or more translations for other input addresses that are stored together with the translation for the specified input address in one node of the B-tree implementing the translation table. During the insertion into the TLB of a translation for a particular input address that was retrieved from the translation table it is determined if there is exactly one valid entry in the TLB that stores a translation for the particular input address. If so, then the translation retrieved from the memory is inserted into that entry, thereby avoiding the creation of multiple TLB entries for the same input address.

Lookaside buffer for address translation in a computer system

A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address, then these entries are invalidated. If the translation table must be searched then the method involves retrieving from the translation table, and inserting into the TLB, a translation for the specified input address and possibly one or more translations for other input addresses stored with the translation for the specified input address in one node of the B-tree implementing the translation table. When a particular input address retrieved from the translation table is inserted into the TLB, it is determined whether there is exactly one valid entry in the TLB that stores a translation for the particular input address If so, then the translation retrieved from the memory is inserted into that entry, and no multiple TLB entries for the same input address are created.

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San Jose, CA, United States of America

Yolin Lih