Motorola Corporation

Yolanda S Musgrove

Olubunmi O Adetutu

Kevin D Lucas

Christopher C Hobbs

Yeong-Jyh Tom Lii

John M Grant

A metal gate structure is formed by depositing a gate dielectric, a gate electrode, a stop layer, and a metal layer within a gate trench and removing the portions of the layers that lie outside the gate trench. A first polish or etch process is used to remove a portion of the metal layer selective to the stop layer. A second polish or etch process is used to remove portions of the gate dielectric, the gate electrode, the stop layer and the metal layer which lie outside the gate trench after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure.

Transistor metal gate structure that minimizes non-planarity effects and method of formation

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (,) over a substrate (,). The MOS metallic gate electrode layer (,) is covered with an ARC layer (,). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (,and,) are then selectively masked photoresist (,) that is selectively exposed to deep ultraviolet (DUV) radiation (,). The ARC layer (,) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

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Pflugerville, TX, United States of America

Yolanda S Musgrove