Lam Research Corporation

Yoko Yamaguchi

Qian Fu

Ramkumar Subramanian

Andrew D Bailey, Iii

Zhongkui Tan

Aaron Eppler

Hua Xiang

Vahid Vahedi

Qing Xu

Jorge Luque

Yoshie Kimura

Mehmet Derya Tetiker

Yassine Kabouzi

Chris Lee

Yasushi Ishikawa

Anne Le Gouil

Juan Valdivia, Iii

Sung Jin Jung

John Edward Daugherty

Mirzafer K Abatchev

Neil M Benjamin

Ying Wu

Richard Alan Gottscho

Tom A Kamp

Alan Jeffrey Miller

David J Cooperberg

Wonchul Lee

Marcus Musselman

Ganesh Upadhyaya

Ce Qin

Qinghua Zhong

Jeff A Bogart

Yiting Zhang

Tae Won Kim

Gladys Lo

Jayoung Choi

Lin Cui

Sangjun Park

Steve Lee

Lisi Xie

Patrick Ponath

Wenchi Liu

Colin Richard Rementer

Indeog Bae

Mehmet Tetiker

Andrew Bailey Iii

A method for patterning a stack having a mask with a plurality of mask features is provided. A targeted deposition is provided, wherein the targeted deposition comprises a plurality of cycles, wherein each cycle comprises flowing a precursor to deposit a layer of precursor and targeted curing the layer of precursor, comprising flowing a curing gas, flowing a modification gas, forming a plasma from the curing gas and modification gas, and exposing the layer of precursor to the plasma providing a targeted curing, wherein plasma from the curing gas cures first portions of the layer of precursor and plasma from the modification gas modifies second portions of the layer of precursor, wherein the modification of the second portion reduces curing of the layer of precursor of the second portions of the layer of precursor. The stack is etched through the targeted deposition.

Method for etching features using a targeted deposition for selective passivation

Methods for forming a vertical growth mask for use in etching applications are described herein. Disclosed embodiments include introducing a tungsten-containing deposition precursor and one or more carrier gases while igniting a plasma to deposit tungsten selectively on field regions of positive features of a patterned etch mask without substantial deposition on sidewalls of the positive features or on an exposed surface of a target layer underlying the patterned etch mask.

Directional deposition in etch chamber

A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.

System and method for determining field non-uniformities of a wafer processing chamber using a wafer processing parameter

Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.

Spacer profile control using atomic layer deposition in a multiple patterning process

A method for etching a tungsten containing layer in an etch chamber is provided. A substrate is placed with a tungsten containing layer in the etch chamber. A plurality of cycles is provided. Each cycle comprises a passivation phase for forming a passivation layer on sidewalls and bottoms of features in the tungsten containing layer. Additionally, each cycle comprises an etch phase for etching features in the tungsten containing layer.

Method of tungsten etching

A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.

System and method for detecting a process point in multi-mode pulse processes

Methods and apparatus for etching substrates using self-limiting reactions based on removal energy thresholds determined by evaluating the material to be etched and the chemistries used to etch the material involve flow of continuous plasma. Process conditions permit controlled, self-limiting anisotropic etching without alternating between chemistries used to etch material on a substrate. A well-controlled etch front allows a synergistic effect of reactive radicals and inert ions to perform the etching, such that material is etched when the substrate is modified by reactive radicals and removed by inert ions, but not etched when material is modified by reactive radicals but no inert ions are present, or when inert ions are present but material is not modified by reactive radicals.

Atomic layer etching in continuous plasma

A method for forming a stair-step structure in a substrate is provided, wherein the substrate has an organic mask, comprising at least one cycle, wherein each cycle comprises a) depositing a hardmask over the organic mask, b) trimming the organic mask, c) etching the substrate, d) trimming the organic mask, wherein there is no depositing a hardmask between etching the substrate and trimming the organic mask, e) etching the substrate, and f) repeating steps a-e a plurality of times forming the stair-step structure.

Hybrid stair-step etch

A method for forming devices with silicon gates over a substrate is provided. Silicon nitride spacers are formed on sides of the silicon gates. An ion implant is provided using the silicon nitride spacers as masks to form ion implant regions. A nonconformal layer is selectively deposited over the spacers and gates that selectively deposits a thicker layer on tops of the gates and spacers and between spacers than on sidewalls of the silicon nitride spacers. Sidewalls of the nonconformal layer are etched away on sidewalls of the silicon nitride spacers. The silicon nitride spacers are trimmed.

Silicon nitride dry trim without top pulldown

A method for etching a multi-layer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the multi-layer resist into the etch chamber. SOgas flows into the etch chamber and a plasma is struck in the etch chamber while flowing the SOgas. The multi-layer resist is then etched.

Method for multi-layer resist plasma etch

An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

Variable temperature processes for tunable electrostatic chuck

Improved methods and apparatus for ion-assisted etch processing in a plasma processing system are disclosed. In accordance with various aspects of the invention, an elevated edge ring, a grooved edge ring, and a RF coupled edge ring are disclosed. The invention operates to improve etch rate uniformity across a substrate (wafer). Etch rate uniformity improvement provided by the invention not only improves fabrication yields but also is cost efficient and does not risk particulate and/or heavy metal contamination.

Techniques for improving etch rate uniformity

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Union City, CA, United States of America

Yoko Yamaguchi