Nec Corporation

Yoko Horiguchi

Kaoru Narita

Takeo Fujii

A semiconductor integrated circuit is provided, which has an improved withstanding voltage for electrostatic breakdown at the time of electrostatic discharge by the charged device model, in the case of protecting a MOS capacitor provided at the input side of the internal circuit. The semiconductor integrated circuit comprises an internal circuitfor inputting an external signal, an internal circuit MOS capacitor, one end of which is connected to a power source wirefor supplying the source voltage and the other end of which is connected to a ground potential wirefor supplying the ground potential; a ground terminalto which one end of the ground potential wire is connected; an electrostatic protection elementconnected in parallel with the MOS capacitorbetween the ground terminaland the MOS capacitor, wherein the MOS capacitor and the electrostatic protection element are connected between the power source wire and the ground potential wire such that the wire resistance Rof the ground potential wire between the ground terminal and the connection point with one end of the electrostatic protection element is larger than the wire resistance Rof the ground potential wire between the connection point with one end of the electrostatic protection element and the connection point with one end of the MOS capacitor.

Semiconductor integrated circuit

The present invention provides an excellent input/output protective device which has a withstand voltage of 200 V or more in device simulation tests according to the EOS/ESD standard. There is presented an input/output device having a protective element that prevents external noise from degrading the internal circuit therein by inducing an electric discharge between diffusion layers of the second conductive type thereof which are disposed on a semiconductor substrate of the first conductive type and facing each other; wherein there are equipped with a plurality of contacts each of which connects a metal wiring layer with a diffusion layer; and a contact at the end section of the protective element on the side of the input section, at least, is provided with a means to increase the resistance thereof so as to make that larger than the resistance of the other contacts.

Input/output protective device

A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

Semiconductor integrated circuit with protection circuit against electrostatic discharge

A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

Semiconductor device and method of making the same

A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.

Semiconductor device with protection circuit

The present invention provides an electrostatic breakdown protecting device which has a high electrostatic breakdown resistance, a high latch up resistance and an excellent protective ability and which has no dead space in the vicinity of protective elements. The present invention includes an I/O terminal directly connected to a protective diode comprising a p-type diffusion layer 103a and an n-type diffusion layer 102b, and an NPN protective bipolar transistor comprising n-type diffusion layers 102b, 102c and a p-type well 113 and connected to an NMOSFET for protection comprising n-type diffusion layers 102c, 102d and a gate electrode 105 via an input resistor 114. These protective elements are formed on the p-type well 113 separated from a substrate for an internal circuit by an n-type buried diffusion layer 111 and an n-type well 112. The internal circuit to be protected is connected to a drain 102d of the NMOSFET for protection.

Semiconductor protection device formed inside a well having contact with

A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor. Besides, the effective channel length of the output transistor is made longer than the effective base width of the protective transistor.

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Tokyo, Japan

Yoko Horiguchi