Toshiba Memory Corporation

Yoko Deguchi

Takuyo Kodama

Yoshihiko Kamata

Kosuke Yanagidaira

Yuki Ishizaki

Tsukasa Kobayashi

Mario Sako

Masahiro Yoshihara

Hiromitsu Komai

Tadashi Yasufuku

Hiroyuki Kaga

Atsushi Okuyama

According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.

Semiconductor memory device

A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.

Semiconductor device including a voltage generation circuit configured with first and second current circuits for increasing voltages of first, second, and third output nodes

A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.

Semiconductor storage device

A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.

Sense amplifier having a sense transistor to which different voltages are applied during sensing and after sensing to correct a variation of the threshold voltage of the sense transistor

According to one embodiment, a semiconductor storage device includes a first plane having a first plurality of memory cells, a second plane having a second plurality of memory cells, first bit lines which are connected to the first plane, second bit lines which are connected to the second plane, a plurality of first sense amplifiers which charge the plurality of first bit lines, and a plurality of second sense amplifiers which charge the plurality of second bit lines. When the first and second planes operate in parallel, a total sum of currents supplied to the plurality of first bit lines from the plurality of first sense amplifiers and currents supplied to the plurality of second bit lines from the plurality of second sense amplifiers reaches a first current value, then decreases to a second current value, and then increases to a third current value.

A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.

Growing community of inventors

Yokohama Kanagawa, Japan

Yoko Deguchi