Hitachi, Ltd.

Yokichi Itoh

Yuji Yatsuda

Shinichi Minami

Takaaki Hagiwara

Ryuji Kondo

Yoshiaki Kamigaki

Hideo Sunami

Tomoyuki Watanabe

Tohru Nakamura

Minoru Nagata

Kenji Kaneko

Takahiro Okabe

Yutaka Okada

Fumiyuki Inose

Toru Toyabe

The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Semiconductor device having aligned semiconductor regions and a

Semiconductor device and method for manufacturing the same

Method for manufacturing a semiconductor device

Method for manufacturing field effect transistors

Method of forming well regions for field effect transistors utilizing

A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

Nonvolatile semiconductor memory

Method of manufacturing field-effect transistors utilizing self-aligned

A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

Nonvolatile MNOS semiconductor memory

An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

I.sup.2 L Memory with nonvolatile storage

A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.

Method for producing a nonvolatile memory device

A shift array for shifting carriers introduced into a semiconductor body toward the X-direction and Y-direction comprises an insulating layer disposed on the semiconductor body, first electrodes disposed on the insulating layer and arranged in a matrix on the X-Y plane, second electrodes disposed between adjacent first electrodes, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each row when carriers are transferred toward the Y-direction, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each column when carriers are transferred toward the X-direction. When carriers are transferred toward the X-direction, the second electrodes disposed between the adjacent first electrodes of each column are biased with a DC voltage whose electrical polarity is reversed relative to the DC voltage applied to the first electrodes for preventing the transit of carriers toward the Y-direction. When carriers are transferred toward the Y-direction, the second electrodes disposed between the adjacent first electrodes of each row are biased with a DC voltage whose polarity is reversed relative to the DC voltage applied to the first electrodes for preventing the transit of carriers toward the X-direction.

Shift array for pattern information processing device utilizing charge

A charge transfer device and method are disclosed in which a plurality of signal charges corresponding to one information input signal are injected into a surface region of a semiconductor substrate beneath specific ones of a plurality of transfer gate electrodes corresponding to said signal charges and transferred therethrough by the transfer gate electrodes. Transferred signal charges subsequent to the first signal charge transferred are detected, thereby using residual charges to prevent decrease in the amount of the detected transfer charges and thus allowing the output signal to appear at the output terminal with a minimum of attenuation even if an increased number of transfer gate electrodes are used.

Information signal transfer method and a charge transfer

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Hachiohji, Japan

Yokichi Itoh