Chartered Semiconductor Manufacturing Ltd (corporation)

Yoke Leng Louis Lim

Dong Kyun Sohn

Sripad Sheshagiri Nagarad

Sung Mun Jung

Siow Lee Chwa

Rachel Low

Dong Hua Liu

Hsiang Fang Lim

Xiao Yu Chen

In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.

Process integration scheme of SONOS technology

A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge storing layer (ONO) from various etches used in the process to pattern the various gate dielectric layers on other regions of substrate.

Method for SONOS EFLASH integrated circuit

Growing community of inventors

Singapore, Singapore

Yoke Leng Louis Lim