Globalfoundries Singapore Pte. Ltd.

Yoke Leng Lim

Siow Lee Chwa

Soh Yun Siah

Yu Jau Chen

Huajun Liu

Yanxia Shao

Eng Huat Toh

Alex See

Wei Lu

Yongshun Sun

Yudi Setiawan

Xuesong Rao

Liang Li

Xinfu Liu

Young Seon You

Suk Hee Jang

Xiaohua Zhan

Xiong Zhang

Anson Heryanto

Sunny Sadana

Martina Damayanti

Abhijit Ghosh

Deepthi Kandasamy

A structure includes a first metal structure including a first upper metal feature having a first sidewall spacer thereabout, and a first lower metal feature under the first upper metal feature. The first lower metal feature includes a sidewall devoid of the first sidewall spacer. The structure also includes a second metal structure spaced from the first metal structure. The second metal structure includes a second upper metal feature having a second sidewall spacer thereabout, and a second lower metal feature under the first upper metal feature. The second lower metal feature includes a sidewall devoid of the second sidewall spacer. A dielectric is between the first metal structure and the second metal structure. The dielectric is devoid of any voids therein, and the opening it fills has a high aspect ratio. A related method is also provided.

Structure with upper features of adjacent metal structures with sidewall spacers providing void-free dielectric filling

Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

Method for making non-volatile memory device

A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.

Reliable pad interconnects

Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.

Integrated circuits with programmable memory and methods for producing the same

Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

Isolation for embedded devices

Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Method of forming split-gate cell for non-volative memory devices

Growing community of inventors

Singapore, Singapore

Yoke Leng Lim