Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Yoji Kashihara

Shigeki Ohbayashi

Motomu Ukita

Takahiro Yokoyama

Hidemoto Tomita

Takashi Izutsu

A control circuit generates burn-in test signals and a signal on the basis of an address for causing transition of a semiconductor memory device to a burn-in test mode to output the signals to a predecoder. The predecoder outputs signals for selecting even-numbered word lines and signals for causing odd-numbered word lines to be in a non-selected state on the basis of the burn-in test signals at H level and further outputs signals for causing even-numbered word lines to be in a non-selected state and signals for selecting odd-numbered word lines on the basis of the burn-in test signals at H level. As a result, stresses can be effectively applied by the burn-in test.

Semiconductor memory device capable of performing burn-in test at high speed

A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.

Semiconductor memory device having divided word line structure

A comparator of a synchronous SRAM includes: n&plus;1 EX-OR gates for detecting whether or not n&plus;1 signals included in an address signal inputted in a cycle and n&plus;1 signals included in an address signal inputted in the next cycle coincide with each other; and wired OR gates receiving output signals of the n&plus;1 EX-OR gates. Accordingly, a detecting speed is faster than in a prior art practice where an OR gate is constituted of NOR gates and NAND gates at multiple stages.

Semiconductor memory device operating in synchronization with clock signal

During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.

Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading

In a test operation for a semiconductor memory device, memory power supply lines are disconnected from a power supply node by using switch gates. Voltages of the memory power supply lines are detected using detection holding circuits. When the detected voltage is lower than a predetermined value, the corresponding memory power supply line is driven to a ground voltage level by the detection holding circuit. Thereby, a standby-current-defective but normally-operable memory cell is forced to an operation-defective state. Then, the standby-current-defective memory cell is identified, and redundancy replacement is performed thereon. Consequently, the standby current abnormality in the semiconductor memory device can be repaired.

Growing community of inventors

Hyogo, Japan

Yoji Kashihara