Elpida Memory, Inc.

Hitachi, Ltd.

Other

Ps4 Luxco S.a.r.l.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Yoji Idei

Kazuhiro Teramoto

Goro Kitsukawa

Takenori Sato

Hiromasa Noda

Kanji Oishi

Akira Ide

Hiroki Fujisawa

Yoji Nishio

Yutaka Uematsu

Yusuke Shimizu

Yoshiro Riho

Seiji Funaba

Hiroaki Nambu

Noriyuki Homma

Hisayuki Higuchi

Susumu Hatano

Yuko Watanabe

Takuyo Kodama

Yoshiaki Sakurai

Kosuke Goto

Ryohei Furuya

A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

Semiconductor device having level shift circuit

A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Semiconductor device having sense amplifier

To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.

Semiconductor device having data input/output unit connected to bus line

A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Semiconductor memory device having input first-stage circuit

A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output.

Power supply voltage dropping circuit using an N-channel transistor output stage

A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

Semiconductor storage device

A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.

Semiconductor device operating in an active mode and a standby mode

A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Semiconductor memory device including a sense amplifier having a reduced operating current

A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

Semiconductor memory device

The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.

Semiconductor device using current mirror circuit

A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits. A first path composed of the first pre-stage delay circuit, first bidirectional delay circuit string and the first post-stage delay circuit and a second path composed of the second pre-stage delay circuit, second bidirectional delay circuit string and the second post-stage delay circuit are alternately switched in an interval of one cycle of the clock signal.

Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof

A 64Mb DRAM includes memory cell array areas , sense amplifier areas , subword driver areas , and cross areas . For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M and the third metal line hierarchy M . The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas . In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Semiconductor device

A 64 Mb DRAM includes memory cell array areas,, sense amplifier areas,, subword driver areas,, and cross areas,. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M,and the third metal line hierarchy M,. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas,in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas,. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

A semiconductor integrated circuit device is provided with an internal circuit which receives a source voltage supplied from an external terminal and is activated based on a voltage obtained by reducing the source voltage, and an output circuit which outputs a signal to be outputted produced by the internal circuit, through an external terminal in accordance with a timing signal. In the semiconductor integrated circuit device, a level shift circuit converts the signal produced by the internal circuit to a signal level corresponding to the level of the source voltage supplied from the external terminal. The output circuit outputs the level-shifted signal therefrom using a timing signal of a voltage level corresponding to the source voltage supplied from the external terminal.

Semiconductor integrated circuit device having step-down voltage circuit

A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.

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Tokyo, Japan

Yoji Idei