Kabushiki Kaisha Toshiba

Yoichiro Takeuchi

Takayuki Yagi

Shinichiro Suzuki

Tadashi Ishikawa

Ikuo Uchihori

Ryuji Sakai

Masahiro Miura

Takaaki Sawada

Yayoi Abe

A computer system for sending out and reproducing at a fixed rate a moving picture file encoded by a moving picture compression scheme using interframe prediction is disclosed. In producing a file for rapid feed or reverse rapid feed from the moving picture file, I-pictures are extracted sequentially from the head of the moving picture file for rapid feed and from the trailing end of the moving picture file for reverse rapid feed thereby to reduce the information by the I-pictures. Digits 0s are padded in place of the I-pictures thus reduced and a designated bit rate for reproduction is stored in the header of the picture file, thereby producing a moving picture file for trick play.

Image processing apparatus and method for realizing trick play

In the distributed control network system, the local control server has a just-in-time compiler with which the user transforms the control for each node described in Java into a code that can be executed on the node at the time of execution. Additionally, the local control server has a functional feature of transforming the protocol so as to make the nodes in its network able to communicate with the nodes in another network having a different protocol. There is also provided means for programming the control to be performed by each node and the flow of processing operations among the nodes in a GUI environment.

Distributed control network system

The present invention provides a compile method comprising steps of allocating a variable which is living and may be used after processing by an exception processing program, to a register whose contents are not changed in delivery processing, during a period of delivery processing when a flow of processing is delivered to the exception processing program written as a part of the program, in case where the exception occurs within a predetermined range of the program, and generating a code corresponding to the delivery processing.

Compile method, a compiler, an exception handler, and a program

A first high-level language source program for a computer of a first architecture is compiled, thereby producing a machine program for a computer of a second architecture. The machine program is decompiled, thereby producing a second high-level language source program which does not depend on any architecture. The second high-level language source program is compiled and linked, thereby producing a first executable load module. Thus, the architecture of the program is converted, and the operation of the machine program is debugged by executing the first executable load module.

Method and apparatus for converting an architecture of a program and

In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction. In the case where an interruption, such as a page fault interruption, which cannot be disabled even in a interrupt disabled state is generated during data processing, processing is resumed from the disable interrupt instruction after the termination of processing for the interruption or an asynchronous interruption, with reference to the address.

Data processing system and method using virtual storage system

An information processing system including an operational processing system having a plurality of registers, for executing an operational processing. A storage system having a memory unit, connected to the operational processing system, stores information stored in the registers into an information region in the memory unit. A memory information storing unit stores information on a stored information region within the information region. The stored information region has already stored information. A input unit inputs the information stored in the registers into the memory unit. And a control unit controls the input unit to control inputting the information stored in the registers into the memory unit according to the information on the stored information region of the memory unit.

Information processing system with control methods and apparatus for

According to this invention, when a program requiring an inseparable operation is to be executed, prior to its program processing, an instruction fetch counter setting instruction is executed by an instruction fetch counter setting unit, and a value indicated by the instruction fetch counter setting instruction, i.e., an instruction count required for the program processing, is set in an instruction fetch counter. The instruction fetch counter is counted down by a count down unit every time an instruction is fetched. When an interrupt is generated, an interrupt control unit refers to the instruction fetch counter. When the reference value is '1' or more, the interrupt is inhibited until the value is set to be '0.'

Asynchronous interrupt inhibit method and apparatus for avoiding

A program execution control system is provided for a processing unit of a computer. An exclusive register has a plurality of 1-bit flag in which true and false data can be individually set and which can individually specify a flag for determining whether execution of each instruction in the program is canceled or not for each instruction. This provides for an integer, logic operation and comparison and a memory for storing an instruction word which contains a flag specifying filed in the exclusive register for determining whether execution of the instruction is canceled or not based on a value stored in the exclusive register, a condition is also provided specifying sub-operation code filed for an operand by use of a numeric value and a flat bit for storing a resulting value of true or false for given condition when the instruction sets the flat for setting the resultant value of truth or falsehood of the condition specified to the instruction of the condition specifying sub-operation code filed in the exclusive flat register specified to the instruction of the flag bit specifying operand field and for canceling the instruction according to at least one of a value of the exclusive register means specified to the instruction of the flat bit specifying filed indicating to cancel the instruction whether the value is '1' or '0'.

Program execution control system

An error information saving apparatus of a computer includes at least one arithmetic unit, a plurality of storage units, and a control unit, connected to the storage units and the arithmetic unit, for controlling these units to perform a predetermined pipeline operation, wherein the storage units comprise an arithmetic register file consisting of a plurality of registers each of which can be designated as a destination operand in a statement of an operation instruction, a status flag string consisting of a plurality of flags provided in a one-to-one correspondence with the registers of the arithmetic register file, and a destination register number holding unit for sequentially saving and holding the numbers of destination registers of all operations performed while error interrupt processing generated after occurrence of an error is delayed by a predetermined time interval, each time one of the operations is completed.

Growing community of inventors

Urawa, Japan

Yoichiro Takeuchi