Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Panasonic Corporation

Other

Matsushita Electric Industrial

Yoichiro Miki

Yuji Sekiguchi

Yoshihiro Kishimoto

Kenta Sokawa

Hiroshi Miyaguchi

Naoya Tokunaga

Atsushi Ishizu

Yuji Yaguchi

Tsuyoshi Akiyama

Masahiro Tani

Kazuki Ninomiya

Masanori Hamada

Masatoshi Nakano

Kenya Adachi

Takashi Yamaguchi

Yoshio Seki

Masaki Tokoi

A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Method and apparatus for timing adjustment

An output of a conventional color-difference inter-field interpolating unit () and an output obtained by a color-difference 4:2:0 inter-field interpolating unit () and a color-difference intra-field line interpolating unit () as a progressive signal through inter-field interpolation by changing a 4:2:2 color-difference signal into a 4:2:0 color-difference signal are switched by a color-difference static image processing method selecting/mixing unit () in accordance with an output or the like of a detecting unit () for detecting a characteristic of an image signal. Thus, it is possible to realize color-difference signal IP conversion static image processing in which degradation of a correct 4:2:2 color-difference signal is suppressed and jaggy is reduced with respect to a 4:2:2 color-difference signal obtained through interpolation of a 4:2:0 signal.

Color difference signal IP conversion method

The video signal processing method of this invention is employed in a video signal processing apparatus that includes a plurality of signal processing parts, each for executing signal processing, for processing two or more digitalized video signals in parallel, and the video signal processing method includes the steps of selecting one or more video signals from the two or more digitalized video signals; and obtaining an object video signal by selecting, from the plurality of signal processing parts, signal processing parts used for signal processing of the selected video signals in accordance with a mode of the object video signal and executing the signal processing in the selected signal processing parts in an order in accordance with the mode of the object video signal.

Multi-input video signal processing method and apparatus

In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to a delay selecting section. A selection part outputs, to a latch circuit, a delayed pulse signal obtained by delaying the latch pulse signal by the front delay circuit. The latch circuit delays the checking data piece from the memory at the reception of the delayed pulse signal. Then, the next data piece is read out from the memory and the selection part outputs, to the latch circuit, a delayed pulse signal delayed by the delay circuit at the preceding stage.

Data latch timing adjustment apparatus

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Memory interface device and memory address generation device

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Growing community of inventors

Osaka, Japan

Yoichiro Miki