Fujitsu Corporation

Yoichiro Ishikawa

Noriyuki Ito

Ryoichi Yamashita

Yasuo Amano

Hiroaki Hanamitsu

Hiroshi Seki

Yukio Makino

Yoshiko Nakanishi

Yumiko Yamanishi

A design support apparatus calculates a crosstalk noise value when a power line does not run parallel, for each of a plurality of sections. Moreover, the design support apparatus calculates a coefficient Fshield that becomes larger with decrease in the area of the power line included in an area between two signal lines based on a relative positional relationship between the two signal lines and the power line in a section, for each of the plurality of sections. Moreover, the design support apparatus corrects the crosstalk noise value corresponding to a section, using the coefficient Fshield corresponding to the section, for each of the plurality of sections. Moreover, the design support apparatus calculates a total of the corrected crosstalk noise values corresponding respectively to the plurality of sections as a crosstalk noise value between the two signal lines.

Support apparatus, design support method, and computer-readable recording medium

A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.

Assisting apparatus, method, and program for checking crosstalk noise between hierarchized modules in a semiconductor circuit

The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement section temporarily arranging a plurality of placement object blocks onto a mounting region so that at least two placement object blocks among the plurality of placement object blocks overlap each other to form an overlap region, and an optimization section changing arrangement of the internal components in at least one placement object block among the placement object blocks forming the overlap region while using the overlap region to optimize at least one placement object block.

Floorplanning apparatus and computer readable recording medium storing floorplanning program

There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip wires to be checked, from which an object wire to be checked and at least one affecting wire are selected, a noise value representing a degree at which the at least one affecting wire induces noise onto the signal of the object wire is calculated and the noise check is performed on the basis of the calculated noise check.

Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored

In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and design automation, when a plurality of cores, comprising same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.

Method for the generation of static noise check data in the layout hierarchical design of an LSI

Noise related to a part of electronic circuits that are to be designed is computed. If the computed noise exceeds a limiting value, parameters of the electronic circuits are modified by using a predetermined method (simple noise check) so that the noise is less than or equal to the limiting value. Signal transmission timing is analyzed for all the electronic circuits, and noise related to all the electronic circuits whose signal transmission timing is analyzed is computed. If the noise exceeds the limiting value, the simple noise check is executed.

Method and device for electronic circuit designing, and computer product

An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.

Integrated circuit design apparatus, method and program evaluating condition of functional blocks, assigned to virtual placement regions in each of lower-and higher-rank mounting blocks

The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire, the last edge appearance timing in the signal waveform of a victim whose noise value exceeds a limit value is compared with the last edge appearance timing in the signal waveform of an aggressor, to evaluate the noise value error in the victim. The apparatus is used in static noise checking of cell arrangement and inter-cell wiring after such cell arrangement and inter-cell wiring are performed at design of integrated circuits such as LSIs.

Noise checking method and apparatus and computer-readable recording medium which records a noise checking program

A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b) obtaining second design data of a rank of hierarchy higher than the predetermined rank of hierarchy; and c) combining the second design data to the first design data.

Design data processing method and recording medium

When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.

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Kawasaki, Japan

Yoichiro Ishikawa