Hitachi, Ltd.

Renesas Technology Corp.

Yoichi Uehara

Seiichi Mita

Takashi Nara

Takushi Nishiya

Ryotaro Kudo

Kenichi Onda

Hiroshi Ide

Tatsuya Hirai

Yoshiju Watanabe

Akihiko Hirano

Kyoichi Hosokawa

Katsumi Yamamoto

Shinichi Yoshida

Hideyuki Yamakawa

Shoichi Miyazawa, Deceased

Kyoko Tsukano

It is aimed at decreasing losses not only in a synchronous rectifier circuit provided at a secondary side of a DC-DC converter, but also in a full-bridge switching circuit provided at a primary side thereof. The DC-DC converter comprises a transformer for voltage conversion, a synchronous rectifier circuit at the secondary side, and a full-bridge switching circuit at the primary side. The DC-DC converter performs synchronous rectifier control which uses switch transistors to change paths of currents flowing through the secondary coil in synchronization with switching operations at the primary side. The DC-DC converter detects currents flowing through a load at the secondary side, primary-side currents varying with the load currents, or primary-side input voltages to dynamically control off-timings of a synchronous rectification transistor at the secondary side. In addition, the DC-DC converter detects primary-side input voltages and currents flowing through the secondary-side load to dynamically control on-timings of a transistor in the primary-side switching circuit.

Switching power supply device and the semiconductor integrated circuit for power supply control

Semiconductor integrated circuit

The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.

Data encoding method for digital data recording and data recording system using the same

A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Digital signal decoding apparatus and a decoding method used therein

Growing community of inventors

Maebashi, Japan

Yoichi Uehara